Physics 623FPGA II: Construction of a ROMDec. 14, 20061 ObjectiveA 32 word 12 bit read-only memory (ROM) is constructed in the Spartan II FPGA and is used todrive three seven-segment displays with a programmed pattern. The ROM is constructed usingthe Xilinx CORE generator and the ROM words are written into the ROM with the COREmemory editor. The ROM addresses are set by a five bit binary counter which is driven with thetest board external 50 MHz clock oscillator. The clock frequency must be stepped down to makethe display visible using, for example, the MSB of a 25 bit binary counter. We will program theROM with the first 32 prime numbers, i.e. 2 through 131 and read it out with the seven-segmentdisplays.2 Procedure OutlineThe top level source will again be a schematic diagram. Since 32 prime numbers takes you intothe hundreds, we have to use all three seven-segment displays and three seven-segment decoders.We will also again use a count-down for the external 50 MHz clock. The 32x12 ROM requires fiveaddress lines so we will need a five bit counter to sequentially address the ROM. While the ROMcan be built direc tly with VHDL coding, we will use a Xilinx tool called the CORE generatorwhich is used to build preconfigured logic functions. Since ISE 6.1 does not support the COREgenerator we must use a newer version of the Xilinx software, ISE 8.2.2.1 Xilinx CoresThe CORE generator can be used to produce devices ranging in complexity from simple arith-metic operators and delay elements to complex building-blocks such as digital signal decoders,processing filters, multiplexers, transformers, FIFOs, and memories.3 Core ImplementationThe Core to be built is treated in the Project Navigator like another type of source. TheCores are built using the CORE generator which can b e run either inside or outside the Projectnavigator. To start the CORE generator outside of the Navigator select Start → P rograms →Xilinx ISEAccessories → CORE Generator. To start the CORE generator from within XilinxISE select NewSource and IP (Coregen&ArchitecturalW izard). The next window will presenta choice of Core types. Choose Memories & StorageElements, then RAMS & ROM s, andthen Distributed M emory v7.1. After executing F inish a window will open up which is atool to construct the memory. Choose ROM, specify the required Depth and Width, go toNext, and then execute Generate. A .xco file will be generated, but remember that the ROMat this point is empty. Now you can run the CORE Ge nerator from within ISE by executingManageCores from the Processes window. Load your Core .cgp Project File and under T ools1select the MemoryEditor. You again specify the depth and width but you will now also be ableto edit the memory contents. Select 2 for the Address Radix (since you will address the ROMin binary) and select 16 for the Data Radix since you will write the memory contents in Hex.Each memory entry will contain three Hex characters corresponding to 12 bits. For example,entering the prime 5 will be entered as 005 and so on. When the memory contents have beenentered, enter a memory Block name and execute Generate under the File menu item. SelectMaking a .coefile. Exit the Memory Editor after saving all the files.4 Creating the BitmapNow Synthesize, Translate, Map, Place and Route as before. In this version of the ISE softwarethe constraints file cannot be edited until Translate has e xecuted. Under Translate you willfind an item Assign Package Pins Post-Translate. Clicking on this will open the Constraints(PACE ) editor. After editing, Implement Design will have to be rerun. After all the greencheckmarks are in place, create the .bit file with Generate Programming File.5 OperationTo enable all the segments of the daughter board seven-segment displays, the file dwnldpa2.svfmust be downloaded into the CPLD on the circuit board. This file is located in the xstools\xsadirectory. Run the circuit and establish that everything is working correctly.6 Questions1. The ROM will be made up out of the Spartan II Block RAM. Our chip has eight BlockRAM cells each of which is a fully synchronous dual-port 4096-bit RAM giving 32 Kbitsof total Block RAM. The rest of the circuit has registers that are made up out of the DFlip-Flops in the CLB. Estimate the number of CLBs required to implement the circuitand compare your estimate to the information in the Project Status Report.2. Determine the maximum clock frequency for the circuit (It better be above 50 MHz). Therequired information is in the Post-Place Static Timing report.3. Now we will look at the performance of the ROM by filtering out everything but the inputsand outputs of the ROM block. Run the Timing Analyzer and once the w indow is openselect Analyze and Against User Specific Paths by Defining Endpoints. Enterthe nets corresponding to the Sources and Destinations of the ROM and run the TimingAnalyzer.What is the worst case access time of the ROM?What is the total worst case delay including nets?27 Circuit Diagram1122334455667788A AB BC CD Dbigromcounterclk count(4:0)counter_1outclkcoutIBUFGCLKleddcdd(3:0) s(6:0)leddcdd(3:0) s(6:0)leddcdd(3:0) s(6:0)32x12 ROMRight LEDLeft LEDMain Board