UA ECE 474 - Lecture Notes (4 pages)

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Lecture Notes



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Lecture Notes

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Lecture Notes


Pages:
4
School:
University of Arizona
Course:
Ece 474 - Computer Aided logic design
Computer Aided logic design Documents

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ECE 274 Digital Logic Lecture 11 Incrementer Counters Multiplier N bit up counter N bit register that can increment add 1 to its own value on each clock cycle Lecture 11 Datapath Components 4 6 Counters cnt tc 010 a 0001 0000 0101 0100 0011 0010 1110 1111 0001 0000 4 bit up counter Terminal last count tc equals1 during value just before rollover cnt ld Internal design 4 bit up counter C 4 0000 0001 0010 0011 1110 1111 0000 Note how count rolls over from 1111 to 0000 10 4 bit register Register incrementer and N input AND gate to detect terminal count a 4 4 1 4 tc 4 C 1 2 Incrementer Incrementer Counter design used incrementer Incrementer design Could use carry ripple adder with B input set to 00 001 But when adding 00 001 to another number the leading 0 s obviously don t need to be considered so just two bits being added per column Can build faster incrementer using combinational logic design process Use half adders adds two bits rather than full adders adds three bits a3 carries unused 011 0011 1 0 0 10 0 a2 a b HA co s a1 a b HA co s a0 a b HA co s 1 a b HA co s t n Capture truth table Derive equation for each output a3 a2 a1 a0 1 co s3s2 s1 s0 r c0 a3a2a1a0 s0 a0 Results in small and fast circuit Note works for small N larger N leads to exponential growth like for N bit adder Inputs a3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 a2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 a1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Outputs a0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 c0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 s3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 s2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 s1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 s0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 I co s3 s2 s1 s0 b a 3 4 Counter Example Mode in Above Design Challenge Mirror Display Not Really a Quiz Design a 2 bit decrementer Recall above mirror display example from Chapter 2 Assumed component that incremented xy input each time button pressed 00 01 10 11 00 01 10 11 00 Can use 2 bit up counter Assumes mode 1 for just one clock cycle during each button press



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