Analog to Digital ConvertersBasic A/D StructureComparitorsSlow-Speed A/D ConvertersSuccessive ApproximationSlide 6Slide 75bit Successive Approximation ADCMore Details on the DACPipeline Algorithmic ADCSelf-Calibrating ADCParallel / Flash A/D ConverterInterpolating ADCsFolding ADCsSchematic of a 5bit Folding ADCFolding CircuitsPowerPoint PresentationSlide 18Two-Step Flash ADCSimple 4-bit Flash ConverterPipelined Flash ADCPart of a Two-Step ADCPIPELINE ADC WITH DIGITAL ERROR CORRECTION12-BIT PIPELINE ADCSlide 25Analog to Digital Converters• Slow (Ramp)• Medium (Successive Approx)• Fast (Flash)• Oversampling ()Key components: Comparitors Sample-and-Hold D/A convertersBasic A/D StructureSampleAnd HoldComparitors(s)D/A(s)Digital OutputsAnalog Input+-Digital ControlComparitors• quantizing unit of ADCs Nonideal aspects:• Input offset voltage (static characteristic)• Propagation time delay- Bandwidth (linear)- Slew rate (nonlinear)Slow-Speed A/D ConvertersSuccessive ApproximationSuccessive ApproximationSuccessive Approximation Algorithm:1.) Start with the MSB bit and work toward the LSB bit.2.) Guess the MSB bit as 1.3.) Apply the digital word 10000.... to a DAC.4.) Compare the DAC output with the sampled analog input voltage.5.) If the DAC output is greater, keep the guess of 1. If the DAC output is less, change the guess to 0.6.) Repeat for the next MSB.If the number of bits is N, the time for conversion will be NT where T is the clock period.Successive Approximation5bit Successive Approximation ADCMore Details on the DACPipeline Algorithmic ADCEach stage: x by 2, + or – by VrefSelf-Calibrating ADCParallel / Flash A/D ConverterNumber of comparator required is 2N-1Typical sampling frequencies can be as high as 400MHz for 6-bits in sub-micron CMOS technology.Interpolating ADCsMust get the gain within ½ LSB accurate.Folding ADCsSchematic of a 5bit Folding ADCFolding CircuitsFolding and interpolation ADCs offer the most resolution at high speeds (≈8 bits at 200MHz)Need discussion for floating-gate Flash ADCsIf no offset at all, then sizing of devices can be optimized for speed. Therefore small input transistors: highest speed, and lowest input capacitance….if smallest cap in a typical 0.35um process, gate input capacitance is approximately 1fF; therefore a 6bit would have an input capacitance of ~100fF with parasitics accounted for, which is small enough…. (would need ~1kOhm output resistance for a S/H to settle in 1nsDo we need S/H block here?Need pictures here.Two-Step Flash ADCSimple 4-bit Flash ConverterPipelined Flash ADCPart of a Two-Step ADCPIPELINE ADC WITH DIGITAL ERROR CORRECTION S/H+-S/H+-ADC-N1 bitDAC-N1 bitS/H+-ADC-N2 bitDAC-N2 bitADC-N3 bitDAC-N3 bitVin2N22N32N1S/HN1 bit REGN3 bit REGN2 bit REGN1 bit REGN2 bit REGN1 bit REG0.5 LSB offset0.5 LSB offsetVREF3 bits3 bits3 bits4 bitsThe ADC of the first stage uses 16 equal capacitors instead of 4 binary weighted for more accuracy12-BIT PIPELINE