UCSD CSE 143 - Lab 3: VHDL Design and Optimization (3 pages)

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Lab 3: VHDL Design and Optimization



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Lab 3: VHDL Design and Optimization

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Pages:
3
School:
University of California, San Diego
Course:
Cse 143 - Microelectronic System Design

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CSE 143 MICROSYSTEM DESIGN WINTER 2008 PROF RAJESH GUPTA Lab 3 VHDL Design and Optimization Due Tuesday Feb 26 2008 at Noon In this third lab you will build a module to simulate data decryption Your module the Decrypter module will interact with two other modules provided to simulate a complete decryption system One module will be the generator module this module will supply data for your module to decrypt The second module is the checker module this module will perform the check of your decrypter data to make sure it was decrypted correctly Coordinating the interaction of all these modules is the testbench module provided Your decrypter module will interact via the other modules with the port list shown below clk in std ulogic reset n in std ulogic databus inout std logic vector 31 downto 0 controlbus inout std logic vector 3 downto 0 A description of these ports are reset n if at any time your design sees the reset n input transition to a LOW value then your design should reset itself to a reset state and stay in the reset state until reset n is no longer low databus the databus is primary means of transferring data between the three modules it is a shared bus and therefore putting information on the bus must be done correctly or else conflicts will arise controlbus the controlbus is the means to read and write different control commands to control the other modules execution The actual data to be decrypted consists of 256 bits The data is referenced in 32 bit increments for decryption and transferred across the databus 32 bits at a time The algorithm for decryption is shown below Data for decryption 256 bits Decrypt data in 32 bit chunks therefore we can consider our data as an array of 8 positions each holding 32 bits of data We can represent this in VHDL as type dataMem is array 7 downto 0 of std ulogic vector 31 downto 0 Decryption Algorithm For each index of our array 0 to 7 do dataArray index dataArray index 7 invert dataArray index 5 least significant bits



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