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Analysis of Jitter due to Power Supply Noise in Phase Locked Loops Payam Heydari Massoud Pedram Department of EE Systems University of Southern California Los Angeles CA 90089 OUTLINE INTRODUCTION PLL NOISE SOURCES POWER SUPPLY NOISE VCO PHASE NOISE PLL TIMING JITTER EXPERIMENTAL RESULTS CONCLUSION 1 INTRODUCTION PLLs are ubiquitous in RF and mixed signal circuits The phase lock concept is fundamental in any situation where some form of feedback is used to synchronize some local periodic event with some observable external event Most high speed microprocessors and memories employ phase locking to suppress timing skews PLL APPLICATIONS Clock and data recovery Clock generation for microprocessors Frequency synthesis Demodulation of FM signals Coherent demodulation of AM signals Local oscillator design for cellular phones cable modems and radios 2 PLL DESIGN SPECIFICATIONS Lock range Capture range Acquisition time Jitter Cycle to cycle jitter T T1 T T2 The PLL timing jitter can cause serious problems in a system which uses the PLL CLK Vin Vin Vout 1 Chld Vout t PRIOR WORK Oscillator phase noise due to the device noise Using an LTI feedback system approach to analyze the phase noise Razavi JSSC 96 Using an LTV model and stochastic differential equations to analyze the phase noise Hajimiri JSSC 98 Demir DAC 98 Oscillator jitter due to power supply noise Using a deterministic frequency modulation model Hertzel CICC 98 3 NOISE SOURCES IN PLL Input noise Phase Detector Input Low pass Filter KDfpd L n vLP L m vPD M KD Frequency Divider t VCO VCO phase noise m m 1 L m bm d m bm 1 d m 1 b0 dt dt n L n 1 an d n an 1 d n 1 a0 dt dt n POWER SUPPLY NOISE Impulsive noise Sinusoidal noise Wp Lp 38 0 25 Wp Lp 38 0 25 Wn Ln 25 0 25 Wn Ln 25 0 25 Cdecoup 0 5pF Cdecoup 100pF Tc Tc 4 MODELING THE SINUSOIDAL NOISE When a large decoupling capacitor is present in the circuit the supply noise is modeled as a sinusoidal waveform with a random maximum amplitude and a uniformly distributed

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