ABSTRACT Title of Thesis: TERPS: THE EMBEDDED RELIABLE PROCESSING SYSTEMAmol Vishwas Gole, Master of Science, 2003Thesis directed by: Professor Bruce L. JacobDepartment of Electrical and Computer EngineeringElectromagnetic Interference (EMI) can have an adverse effect on commercial electronics. As feature sizes of integrated circuits become smaller, their susceptibility to EMI increases. In light of this, integrated circuits will face substantial problems in the future either from electromagnetic disturbances or intentionally generated EMI from a malicious source. The Embedded Reliable Processing System (TERPS) is a fault tolerant system architecture which can significantly reduce the threat of EMI in computer systems. TERPS employs a checkpoint and rollback recovery mechanism tied with a multi-phase commit protocol and 3D IC technology. This enables it to recover from substantial EMI without having to shutdown or reboot. In the face of such EMI, only a loss in performance dictated by the strength and duration of the interference and the frequency of checkpointing will be seen. Various conditions in which chips can fail under the influence of EMI are described. The checkpoint and rollback recovery mechanism and the resulting TERPS architecture isstipulated. A thorough evaluation of the design correctness is provided. The technique is implemented in Verilog HDL using a 16-bit, 5-stage pipelined processor to show proof of concept. The performance overhead is calculated for different checkpointing intervals and is shown to be very reasonable (5-6% for checkpointing every 128 CPU cycles).TERPS: THE EMBEDDED RELIABLE PROCESSING SYSTEM byAmol Vishwas GoleThesis submitted to the Faculty of the Graduate School of the University of Maryland, College Park in partial fulfillmentof the requirements for the degree ofMaster of Science2003Advisory Committee:Professor Bruce L. Jacob, Chair/AdvisorProfessor Virgil D. GligorProfessor Manoj Franklin© Copyright by Amol Vishwas Gole2003ii DEDICATION To my beloved parents, Lata and Vishwasandand all my family and friendsiii ACKNOWLEDGEMENTS I am grateful to my advisor, Dr. Bruce Jacob, for his direction and encouragement for the past two wonderful years here at the University of Maryland. He has not only been a great academic advisor to me, but has afforded invaluable guidance and insight to life and its many little quirks. I am sure the knowledge I have gained as being a research assistant and student under Dr. Jacob’s supervision will help me throughout my professional career. This work would not have been possible without him. Further, I would like to express my gratitude towards Dr. Franklin and Dr. Gligor for agreeing to be on my committee. I would also like to thank Dr. Declaris and Dr. Gansman for their support and the experience I gained as a teaching assistant under them. I would like to especially thank Dr. Declaris for always believing in me and his precious guidance. I would also like to thank the University, the teachers, and the staff for making my Masters Degree a reality. Working with Cagdas, Sam, and Xia has been a great experience and I would like to particularly thank them for helping me with this work. I am grateful to Sada and IyerB for lending their time and ideas when it really counted. I would like to thank my roommates and friends, Mukul, Spawgi, Anibha, Potti, Chandesaab, Arindam, Hyma, and Priya for all the support, laughter, dabbas, and putting up with the “Gole Factor” these last few years. I would like to especially thank Spawgi, Potti, and Priya for being very understanding and caring during these last few months. I couldn’t have done it without you guys and I hope our friendship lasts forever.Finally I am indebted to my beloved parents, Lata and Vishwas, my sister and brother-in-law, Tina and Vikram, and all my relatives for believing in me and supporting me throughout especially during the difficult times.iv TABLE OF CONTENTS List of Figures........................................................................................................... viList of Tables ..........................................................................................................viiiChapter 1 Introduction ....................................................................................... 11.1 Effect of EMI on Integrated Circuits..................................................... 11.2 TERPS Architecture ...............................................................................4Chapter 2 Related Work ..................................................................................... 8Chapter 3 TERPS Architecture ........................................................................ 183.1 Checkpointing.......................................................................................183.2 Rollback Recovery................................................................................24Chapter 4 Correctness of Design ......................................................................264.1 Resuming to a Consistent State............................................................274.1.1 System State and Rollback.......................................................274.1.2 Precise Checkpointing..............................................................284.1.3 Multi-phase Commit ................................................................294.2 Re-execution of instructions.................................................................34Chapter 5 Implementation ................................................................................ 375.1 Basic Processor Architecture................................................................375.2 Implementation.....................................................................................395.2.1 Logical Verification..................................................................435.3 Safe Storage Implementation ...............................................................46vChapter 6 Results ..............................................................................................516.1 Performance Analysis...........................................................................516.1.1 Performance with the Memory Controller on-chip.................54Chapter 7 Conclusions and Future Work ......................................................... 56References