UNC-Chapel Hill COMP 206 - Instruction-Level Parallelism (Multiple-Issue, Speculation) (23 pages)

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Instruction-Level Parallelism (Multiple-Issue, Speculation)



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Instruction-Level Parallelism (Multiple-Issue, Speculation)

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Lecture Notes


Pages:
23
School:
University of North Carolina at Chapel Hill
Course:
Comp 206 - Computer Architecture and Implementation

Unformatted text preview:

COMP 206 Computer Architecture and Implementation Montek Singh Wed Oct 22 2003 Topic Instruction Level Parallelism 1 Multiple Issue Speculation contd Outline Multiple Issue Architectures Superscalar processors VLIW very long instruction word processors Scheduling Statically scheduled using compiler techniques Dynamically scheduled using variants of Tomasulo s alg Reading HP3 Sections 3 6 3 7 2 Multiple Issue Eliminating data and control stalls can achieve CPI of 1 Can we decrease CPI below 1 Not if we issue only one instruction per clock cycle Multiple issue processors allow multiple instructions to issue in a clock cycle Superscalar issue varying numbers of instructions per clock dynamic issue Statically scheduled by compiler Dynamically scheduled by hardware VLIW issue fixed number of instructions per clock static issue Statically scheduled by compiler Examples Superscalar IBM PowerPC Sun SuperSPARC DEC Alpha HP 8000 VLIW Intel HP Itanium 3 A Superscalar Version of MIPS Two instructions can be issued per clock cycle One can be load store branch integer operation Other can be any FP operation Need to fetch and decode 64 bits per cycle Instructions paired and aligned on 64 bit boundary Integer instruction appears first Dynamic issue First instruction issues if independent and satisfies other criteria Second instruction issues only if first one does and is independent and satisfies similar criteria Limitation One cycle delay for loads and branches now turns into three instruction delay because instructions are now squeezed closer together 4 Performance of Static Superscalar LOOP LOOP LD LD ADDD ADDD SD SD SUBI SUBI BNEZ BNEZ F0 F0 0 R1 0 R1 F4 F4 F0 F0 F2 F2 0 R1 F4 0 R1 F4 R1 R1 R1 R1 88 R1 R1 LOOP LOOP LOOP LOOP LD LD F0 F0 0 R1 0 R1 LD F6 8 R1 LD F6 8 R1 LD LD F10 F10 16 R1 16 R1 LD LD F14 F14 24 R1 24 R1 LD F18 32 R1 LD F18 32 R1 SD SD 0 R1 0 R1 F4 F4 SD 8 R1 SD 8 R1 F8 F8 SD SD 16 R1 16 R1 F12 F12 SUBI R1 R1 SUBI R1 R1 40 40 SD 16 R1 F16 SD 16 R1 F16 BNEZ BNEZ



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