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2008 Military Aerospace Programmable Logic Devices MAPLD Conference Sept 15 18 2008 Annapolis MD A Power Efficient Design Approach to Radiation Hardened Digital Circuitry using Dynamically Selectable Triple Modulo Redundancy Brock J LaMeres and Clint Gauer Department of Electrical and Computer Engineering Montana State University Bozeman MT 59717 USA Abstract Triple Modulo Redundancy TMR is one of the most common techniques for fault mitigation in digital systems TMR based computing has a natural application to mission critical systems for military and aerospace applications which are exposed to cosmic radiation and are susceptible to Single Event Upsets SEUs TMR s increased immunity to SEUs comes at the expense of increased power consumption and area This paper presents a dynamically selectable TMR architecture which can be used to reduce power consumption when radiation levels are low We apply this architecture to a test system in order to evaluate its power reduction and area overhead compared to a traditional static TMR approach We show that the dynamically selectable TMR can be adopted with only a 2 2 increase in equivalent gate count compared to the traditional static TMR when implemented on a Xilinx Virtex 4 FPGA This approach yields as much as a 67 reduction in power consumption versus a traditional static TMR approach when radiation levels are low I INTRODUCTION Recently there has been an increased interest in the radiation immunity of digital circuitry for use in aerospace and military applications 1 2 This renewed interest comes as a result of two main factors The first is the widening gap between the performance of commercial off the shelf COTS integrated circuits and those that are fabricated with the ability to withstand the radiation levels of an extraterrestrial environment 3 The second reason is that the number of foundries providing radiation hardened RadHard processes is diminishing due to a reduction in post cold war Department of Defense funding

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