CpE 242 Computer Architecture and Engineering Busses and OS’s ResponsibilitiesRecap: IO Benchmarks and I/O DevicesOutline of Today’s LectureThe Big Picture: Where are We Now?Buses: Connecting I/O to Processor and MemoryAdvantages of BusesDisadvantages of BusesThe General Organization of a BusMaster versus SlaveOutput OperationInput OperationTypes of BusesA Computer System with One Bus: Backplane BusA Two-Bus SystemA Three-Bus SystemSynchronous and Asynchronous BusA Handshaking ProtocolIncreasing the Bus BandwidthObtaining Access to the BusMultiple Potential Bus Masters: the Need for ArbitrationThe Daisy Chain Bus Arbitrations SchemeCentralized Arbitration with a Bus ArbiterSimple Implementation of a Bus ArbiterPriority LogicJK Flip FlopSlide 26Responsibilities of the Operating SystemOperating System RequirementsOS and I/O Systems Communication RequirementsGiving Commands to I/O DevicesI/O Device Notifying the OSPolling: Programmed I/OInterrupt Driven Data TransferI/O InterruptInterrupt LogicProgram Interrupt/Exception HardwareProgrammer’s ViewDelegating I/O Responsibility from the CPU: DMADelegating I/O Responsibility from the CPU: IOPSummary:Where to get more information?cs 152 buses.1©DAP & SIK 1995CpE 242Computer Architecture and EngineeringBusses and OS’s Responsibilitiescs 152 buses.2©DAP & SIK 1995Recap: IO Benchmarks and I/O Devices°Disk I/O Benchmarks:•Supercomputer Application: main concern is data rate•Transaction Processing: main concern is I/O rate•File System: main concern is file access°Three Components of Disk Access Time:•Seek Time: advertised to be 12 to 20ms. May be lower in real life.•Rotational Latency: 5.6 ms at 5400 RPM and 8.3 ms at 3600 RPM•Transfer Time: 2 to 4 MB per second°Graphic Display:•Resolution: (M pixels) x (N scan lines)•Frame Buffer size and bandwidth requirement can be reduced byplacing a Color Map between the Frame Buffer and CRT display•VRAM: a DRAM core with a high speed shift registerMNcs 152 buses.3©DAP & SIK 1995Outline of Today’s Lecture°Recap and Introduction (5 minutes)° Introduction to Buses (15 minutes)°Bus Types and Bus Operation (10 minutes)°Bus Arbitration and How to Design a Bus Arbiter (15 minutes)°Operating System’s Role (15 minutes)°Delegating I/O Responsibility from the CPU (5 minutes)°Summary (5 minutes)cs 152 buses.4©DAP & SIK 1995The Big Picture: Where are We Now?ControlDatapathMemoryProcessorInputOutput°Today’s Topic: How to connect I/O to the rest of the computer?ControlDatapathMemoryProcessorInputOutputNetworkcs 152 buses.5©DAP & SIK 1995Buses: Connecting I/O to Processor and Memory°A bus is a shared communication link°It uses one set of wires to connect multiple subsystemsControlDatapathMemoryProcessorInputOutputcs 152 buses.6©DAP & SIK 1995Advantages of Buses°Versatility:•New devices can be added easily•Peripherals can be moved between computersystems that use the same bus standard°Low Cost:•A single set of wires is shared in multiple waysMemoryProcessorI/O DeviceI/O DeviceI/O Devicecs 152 buses.7©DAP & SIK 1995Disadvantages of Buses°It creates a communication bottleneck•The bandwidth of that bus can limit the maximum I/O throughput°The maximum bus speed is largely limited by:•The length of the bus•The number of devices on the bus•The need to support a range of devices with:-Widely varying latencies -Widely varying data transfer ratesMemoryProcessorI/O DeviceI/O DeviceI/O Devicecs 152 buses.8©DAP & SIK 1995The General Organization of a Bus°Control lines:•Signal requests and acknowledgments•Indicate what type of information is on the data lines°Data lines carry information between the source and the destination:•Data and Addresses•Complex commands°A bus transaction includes two parts:•Sending the address•Receiving or sending the dataData LinesControl Linescs 152 buses.9©DAP & SIK 1995Master versus Slave°A bus transaction includes two parts:•Sending the address•Receiving or sending the data°Master is the one who starts the bus transaction by:•Sending the address°Salve is the one who responds to the address by:•Sending data to the master if the master ask for data•Receiving data from the master if the master wants to send dataBusMasterBusSlaveMaster send addressData can go either waycs 152 buses.10©DAP & SIK 1995Output Operation°Output is defined as the Processor sending data to the I/O device:ProcessorControl (Memory Read Request)MemoryStep 1: Request MemoryI/O Device (Disk)Data (Memory Address)ProcessorControlMemoryStep 2: Read MemoryI/O Device (Disk)DataProcessorControl (Device Write Request)MemoryStep 3: Send Data to I/O DeviceI/O Device (Disk)Data (I/O Device Address and then Data)cs 152 buses.11©DAP & SIK 1995Input Operation°Input is defined as the Processor receiving data from the I/O device:ProcessorControl (Memory Write Request)MemoryStep 1: Request MemoryI/O Device (Disk)Data (Memory Address)ProcessorControl (I/O Read Request)MemoryStep 2: Receive DataI/O Device (Disk)Data(I/O Device Addressand then Data)cs 152 buses.12©DAP & SIK 1995Types of Buses°Processor-Memory Bus (design specific)•Short and high speed•Only need to match the memory system-Maximize memory-to-processor bandwidth•Connects directly to the processor°I/O Bus (industry standard)•Usually is lengthy and slower•Need to match a wide range of I/O devices•Connects to the processor-memory bus or backplane bus°Backplane Bus (industry standard)•Backplane: an interconnection structure within the chassis•Allow processors, memory, and I/O devices to coexist•Cost advantage: one single bus for all componentscs 152 buses.13©DAP & SIK 1995A Computer System with One Bus: Backplane Bus°A single bus (the backplane bus) is used for:•Processor to memory communication•Communication between I/O devices and memory°Advantages: Simple and low cost°Disadvantages: slow and the bus can become a major bottleneck°Example: IBM PCProcessor MemoryI/O DevicesBackplane Buscs 152 buses.14©DAP & SIK 1995A Two-Bus System°I/O buses tap into the processor-memory bus via bus adaptors:•Processor-memory bus: mainly for processor-memory traffic•I/O buses: provide expansion slots for I/O devices°Apple Macintosh-II•NuBus: Processor, memory, and a few selected I/O devices•SCCI Bus: the rest of the I/O devicesProcessor MemoryI/OBusProcessor Memory BusBusAdaptorBusAdaptorBusAdaptorI/OBusI/OBuscs 152 buses.15©DAP & SIK 1995A