Central Processing UnitTopicsInternal Architecture of a CPU (Z80)Fetch and Execute CyclesMicrocontroller approach (fig.2.7)Instruction formatsAddressing ModesRISC vs CISCRISC vs. CISCMemoryMemory Access01/14/19 1Central Processing UnitChapter 2201/14/19TopicsCentral processing unitInternal architectureFetch and execute cyclesMicrocontrollersInstruction formatsCore instructionsAddressing modesRISC vs CISCMemoryMemory AccessMemory TechnologiesMemory hierarchyMemory OrganizationInput/OutputProgrammed IODirect memory access (DMA)Memory mapped IOInterruptsProgrammable Interrupt controllerInterfacing devices to CPU via interrupts301/14/19Internal Architecture of a CPU (Z80)401/14/19Fetch and Execute CyclesMacro instructions are fetched from memory and executed.Fetch and execute cycles: simple overlap.501/14/19Microcontroller approach (fig.2.7)Microcontroller is a internal processor that is programmable via microinstructions.This approach is highly relevant to real-time systems and devices since each macro instruction is mapped into a set of microinstructions that can be directly executed with decoding etc.Fine grained instructions are in micro memory and are wider than macro instructions.These microinstructions directly control the logic gates of the microcontroller.Microcontroller can take direct input from devices and can signal directly to devices.High level language support is available for software development using microcontrollers.Examples: Intel 8051, 8748, MCS 51/251See http://www.intel.com/design/embcontrol/index.htm601/14/19Instruction formats1, 0 address forms (implicit operands, destination); example: pop2-address forms: arithmetic operations3-address formsCore instructions:Horizontal bit operations: XOR, AND, NOTVertical bit operations: rotate right, rotate leftControl: trap, cli, epi, dpi, haltData movement: store/loadMath/special processing: add, sub, bts (lock)701/14/19Addressing ModesImmediateDirect memoryIndirect memoryRegisterAuto-increment, auto-decrement801/14/19RISC vs CISCCISC (complex instruction set computer)Complex instructions: multiple cyclesAny instruction can ref memoryNo instructions are pipelinedMicro-program for native instructionVariable format instructionsMultiple instructions and addressing modeSingle set of registersComplexity is in the micro-program and hardware901/14/19RISC vs. CISCRISC (reduced instruction set computer)Complementary set of first eight CISC principlesSimple single cycle instructionsLoad/store only can reference memoryHighly pipelinedInstructions directly executed by hardwareFixed-format instructionsFew instructions and addressing modesLarge multiple set of registersComplexity handled by the compiler and softwareAdvantage for real-time system: average instruction execution time is lower than ciscDisadvantage: associated with cache and elaborate multistage pipeline, while this improves performance for average case, pathological (extreme) situations may not be handled satisfactorily. Many real-time systems typically encounter extreme conditions.1001/14/19MemoryMemory access time: interval between when a datum is requested and when it is available to the CPU.This can have profound effect on real-time performance.Real access time is decided by the physical characteristic of the memory chosen.Effective access time depends on type, memory technology, memory layout (ex: memory interleaving), and buffering etc.1101/14/19Memory AccessTypical microprocessor read cycle embodies the handshaking between the processor and main memory store.1. CPU places address on address bus and allows signal to settle.2. Then it places appropriate data on the data bus.3. CPU asserts ALE (Address Latch enable)4. CPU sends out WR signal5. Memory device is selected and the data is written to the addressed locationAll are synchronized to the system
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