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SJSU EE 166 - Eadder_verification

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1Kogge Stone Adder Logic VerificationD. W. Parent2This example shows how the logic was verified of a Kogge Stone Adder• The Major Steps were:– Convert grey and black cells to schematics– Convert “tree” diagrams into a schematic– Create a trusted adder– Compare trusted adder to “new adder”3Black Cell• When doing a completely new logic just use the digital parts in the NCSU kit!SchematicSymbolMake sure toedit the labelsso that they can beseen in a largeSchematic.4Grey CellSchematicSymbolA Grey cell is a Black cellwithout the grouppropagate• Once could use AOI or NAND NAND to implement these cells.5Tree Diagram of KS adder from David Harris68 bit KS adder schematic with carry in and carry out7Does this adder work properly?• Boolean logic analysis would be great to try and show the equivalence of a ripple, or carry look ahead adder to a KS• Not my strong suit.8Create and verify a 1 bit full adder9Create a 8bit trusted adder10Create a 9 bit bit-wise XORThis will be used to compare the carry outand sum signals of both adders.11Create a test bench that willfeed the same test vectors into both adders and compare their outputs.KS ADDER12Run KS adder against “Trusted”adder• Search for “1”’. If signals are different then XOR will give one.Can not really see if there is a “1” value at this time scale.13Export Data Into Text• NC verilog tracks the changes only. WE can see that no signal was a “1” and since we did all test vectors the adders are logically equivalent.This is all the data.14Summary• This technique was used to finally verify a KS adder structure.• There is a reason the adder was labeled “adder3”• This was not an efficient method of verification– Program adder!– Use Boolean logic!– It still


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SJSU EE 166 - Eadder_verification

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