(TOP VIEW)positive logic: Low input to clear resets Q low andpositive logic: Q high regardless of dc levels at Apositive logic: or B inputs.14 13 12 11 10 9123456716 158VCC1A1 Rext/Cext1Cext1Q 2Q2B2CLR2A1B 1CLR1Q2Q 2Cext2 Rext/CextGNDQQCLRQQCLR+VCCRextR/CCext*See operational notes — Pulse Trigger Modes5-1FAST AND LS TTL DATADUAL MONOSTABLEMULTIVIBRATORSWITH SCHMITT-TRIGGER INPUTSEach multivibrator of the LS221 features a negative-transition-triggeredinput and a positive-transition-triggered input either of which can be used asan inhibit input.Pulse triggering occurs at a voltage level and is not related to the transitiontime of the input pulse. Schmitt-trigger input circuitry for B input allowsjitter-free triggering for inputs as slow as 1 volt/second, providing the circuitwith excellent noise immunity. A high immunity to VCC noise is also providedby internal latching circuitry.Once triggered, the outputs are independent of further transitions of theinputs and are a function of the timing components. The output pulses can beterminated by the overriding clear. Input pulse width may be of any durationrelative to the output pulse width. Output pulse width may be varied from 35nanoseconds to a maximum of 70 s by choosing appropriate timingcomponents. With Rext = 2.0 kΩ and Cext = 0, a typical output pulse of 30nanoseconds is achieved. Output rise and fall times are independent of pulselength.Pulse width stability is achieved through internal compensation and isvirtually independent of VCC and temperature. In most applications, pulsestability will only be limited by the accuracy of external timing components.Jitter-free operation is maintained over the full temperature and VCC rangesfor greater than six decades of timing capacitance (10 pF to 10 µF), andgreater than one decade of timing resistance (2.0 to 70 kΩ for theSN54LS221, and 2.0 to 100 kΩ for the SN74LS221). Pulse width is definedby the relationship: tw(out) = CextRext ln 2.0 ≈ 0.7 Cext Rext; where tW is in nsif Cext is in pF and Rext is in kΩ. If pulse cutoff is not critical, capacitance upto 1000 µF and resistance as low as 1.4 kΩ may be used. The range ofjitter-free pulse widths is extended if VCC is 5.0 V and 25°C temperature.• SN54LS221 and SN74LS221 is a Dual Highly Stable One-Shot• Overriding Clear Terminates Output Pulse• Pin Out is Identical to SN54/74LS123FUNCTION TABLE(EACH MONOSTABLE)INPUTS OUTPUTSCLEAR A B Q QL X X L HX H XL HXXLL HHL°H±H*°LHTYPETYPICALPOWERMAXIMUMOUTPUT PULSEDISSIPATION LENGTHSN54LS221 23 mW 49 sSN74LS221 23 mW 70 sSN54/74LS221DUAL MONOSTABLEMULTIVIBRATORSWITH SCHMITT-TRIGGER INPUTSLOW POWER SCHOTTKYJ SUFFIXCERAMICCASE 620-09N SUFFIXPLASTICCASE 648-08161161ORDERING INFORMATIONSN54LSXXXJ CeramicSN74LSXXXN PlasticSN74LSXXXD SOIC161D SUFFIXSOICCASE 751B-035-2FAST AND LS TTL DATASN54/74LS221OPERATIONAL NOTESOnce in the pulse trigger mode, the output pulse width isdetermined by tW = RextCextIn2, as long as Rext and Cext arewithin their minimum and maximum valves and the duty cycleis less than 50%. This pulse width is essentially independentof VCC and temperature variations. Output pulse widths variestypically no more than ±0.5% from device to device.tWTIf the duty cycle, defined as being 100• where T is theinputperiod of the input pulse, rises above 50%, the output pulsewidth will become shorter. If the duty cycle varies betweenlow and high valves, this causes the output pulse width tovary in length, or jitter. To reduce jitter to a minimum, Rextshould be as large as possible. (Jitter is independent of Cext).With Rext = 100K, jitter is not appreciable until the duty cycleapproaches 90%.Although the LS221 is pin-for-pin compatible with theLS123, it should be remembered that they are not functionallyidentical. The LS123 is retriggerable so that the output isdependent upon the input transitions once it is high. This is notthe case for the LS221. Also note that it is recommended toexternally ground the LS123 Cext pin. However, this cannot bedone on the LS221.The SN54LS/74LS221 is a dual, monolithic, non-retrigger-able, high-stability one shot. The output pulse width, tW can bevaried over 9 decades of timing by proper selection of theexternal timing components, Rext and Cext.Pulse triggering occurs at a voltage level and is, therefore,independent of the input slew rate. Although all three inputshave this Schmitt-trigger effect, only the B input should beused for very long transition triggers (≥1.0 µV/s). Highimmunity to VCC noise (typically 1.5 V) is achieved by internallatching circuitry. However, standard VCC bypassing isstrongly recommended.The LS221 has four basic modes of operation.Clear Mode: If the clear input is held low, irregardless ofthe previous output state and other inputstates, the Q output is low.Inhibit Mode: If either the A input is high or the B input islow, once the Q output goes low, it cannot beretriggered by other inputs.Pulse TriggerMode: A transition of the A or B inputs as indicatedin the functional truth table will trigger the Qoutput to go high for a duration determinedby the tW equation described above; Q willgo low for a corresponding length of time.The Clear input may also be used to triggeran output pulse, but special logic precondi-tioning on the A or B inputs must be done asfollows:Following any output triggering actionusing the A or B inputs, the A input mustbe set high OR the B input must be setlow to allow Clear to be used as a trigger.Inputs should then be set up per the truthtable (without triggering the output) toallow Clear to be used a trigger for theoutput pulse.If the Clear pin is routinely being used totrigger the output pulse, the A or B inputsmust be toggled as described abovebefore and between each Clear triggerevent.Once triggered, as long as the outputremains high, all input transitions (exceptoverriding Clear) are ignored.OverridingClear Mode: If the Q output is high, it may be forced lowby bringing the clear input low.5-3FAST AND LS TTL DATASN54/74LS221GUARANTEED OPERATING RANGESSymbol Parameter Min Typ Max UnitVCCSupply Voltage 54744.54.755.05.05.55.25VTAOperating Ambient Temperature Range 5474–550252512570°CIOHOutput Current — High 54, 74 –0.4 mAIOLOutput Current — Low 54744.08.0mADC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)SblPLimitsUiT C di iSymbol ParameterMin Typ MaxUnit Test ConditionsVT+Positive-Going ThresholdVoltage at C Input1.0 2.0 V VCC = MINVTNegative-Going