TMS320x2833x, 2823x Direct Memory Access (DMA) ModuleTable of ContentsPreface1 Introduction2 Architecture2.1 Block Diagram2.2 Peripheral Interrupt Event Trigger Sources2.3 DMA Bus3 Pipeline Timing and Throughput4 CPU Arbitration4.1 For the External Memory Interface (XINTF) Zones4.2 For All Other Peripherals/Memories5 Channel Priority5.1 Round-Robin Mode5.2 Channel 1 High Priority Mode6 Address Pointer and Transfer Control7 ADC Sync Feature8 Overrun Detection Feature9 Register Descriptions9.1 DMA Control Register (DMACTRL) — EALLOW Protected9.2 Debug Control Register (DEBUGCTRL) — EALLOW Protected9.3 Revision Register (REVISION)9.4 Priority Control Register 1 (PRIORITYCTRL1) — EALLOW Protected9.5 Priority Status Register (PRIORITYSTAT)9.6 Mode Register (MODE) — EALLOW Protected9.7 Control Register (CONTROL) — EALLOW Protected9.8 Burst Size Register (BURST_SIZE) — EALLOW Protected9.9 BURST_COUNT Register9.10 Source Burst Step Register Size (SRC_BURST_STEP) — EALLOW Protected9.11 Destination Burst Step Register Size (DST_BURST_STEP) — EALLOW Protected9.12 Transfer Size Register (TRANSFER_SIZE) — EALLOW Protected9.13 Transfer Count Register (TRANSFER_COUNT)9.14 Source Transfer Step Size Register (SRC_TRANSFER_STEP) — EALLOW Protected9.15 Destination Transfer Step Size Register (DST_TRANSFER_STEP) — EALLOW Protected9.16 Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) — EALLOW protected)9.17 Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT)9.18 Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) — EALLOW Protected9.19 Shadow Source Begin and Current Address Pointer Registers (SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW) — All EALLOW Protected9.20 Active Source Begin and Current Address Pointer Registers (SRC_BEG_ADDR/DST_BEG_ADDR)9.21 Shadow Destination Begin and Current Address Pointer Registers (SRC_ADDR_SHADOW/DST_ADDR_SHADOW) — All EALLOW Protected9.22 Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR)Appendix A Revision HistoryTMS320x2833x, 2823x Direct Memory Access(DMA) ModuleReference GuideLiterature Number: SPRUFB8DSeptember 2007–Revised April 20112SPRUFB8D–September 2007–Revised April 2011Submit Documentation Feedback© 2007–2011, Texas Instruments IncorporatedPreface ....................................................................................................................................... 61 Introduction ........................................................................................................................ 82 Architecture ...................................................................................................................... 102.1 Block Diagram .......................................................................................................... 102.2 Peripheral Interrupt Event Trigger Sources ........................................................................ 102.3 DMA Bus ................................................................................................................ 133 Pipeline Timing and Throughput ......................................................................................... 134 CPU Arbitration ................................................................................................................. 154.1 For the External Memory Interface (XINTF) Zones ............................................................... 154.2 For All Other Peripherals/Memories ................................................................................. 165 Channel Priority ................................................................................................................ 165.1 Round-Robin Mode .................................................................................................... 165.2 Channel 1 High Priority Mode ........................................................................................ 176 Address Pointer and Transfer Control .................................................................................. 177 ADC Sync Feature ............................................................................................................. 228 Overrun Detection Feature .................................................................................................. 249 Register Descriptions ........................................................................................................ 259.1 DMA Control Register (DMACTRL) — EALLOW Protected ..................................................... 269.2 Debug Control Register (DEBUGCTRL) — EALLOW Protected ................................................ 279.3 Revision Register (REVISION) ....................................................................................... 279.4 Priority Control Register 1 (PRIORITYCTRL1) — EALLOW Protected ........................................ 289.5 Priority Status Register (PRIORITYSTAT) ......................................................................... 299.6 Mode Register (MODE) — EALLOW Protected ................................................................... 309.7 Control Register (CONTROL) — EALLOW Protected ............................................................ 329.8 Burst Size Register (BURST_SIZE) — EALLOW Protected ..................................................... 349.9 BURST_COUNT Register ............................................................................................ 349.10 Source Burst Step Register Size (SRC_BURST_STEP) — EALLOW Protected ............................. 359.11 Destination Burst Step Register Size (DST_BURST_STEP) — EALLOW Protected ........................ 369.12 Transfer Size Register (TRANSFER_SIZE) — EALLOW Protected ............................................ 369.13 Transfer Count Register (TRANSFER_COUNT) .................................................................. 379.14 Source Transfer Step Size Register (SRC_TRANSFER_STEP) — EALLOW Protected .................... 379.15 Destination Transfer Step Size Register (DST_TRANSFER_STEP) — EALLOW Protected ............... 389.16 Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) — EALLOW protected) ................ 389.17 Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT) ....................................... 399.18 Source/Destination