PowerPoint PresentationSlide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Slide 39Slide 40Slide 41Slide 42Slide 43Slide 44Slide 45Slide 46Slide 47Slide 48Slide 49Slide 50Slide 51Slide 52Slide 53Slide 54Slide 55Slide 56Slide 57Slide 58Slide 59Slide 60Slide 61Slide 62Slide 63Slide 64Slide 65Slide 66Slide 67Slide 68Slide 69Slide 70Slide 71Slide 72Slide 73Slide 74Slide 75Slide 76Slide 77Slide 78Slide 79Slide 80Slide 81Slide 82Slide 83Slide 84Slide 85Slide 86Slide 87Slide 88Slide 89Slide 90Slide 91Slide 92Slide 93Slide 94Slide 95Slide 96Slide 97Slide 98Slide 99Slide 100Slide 101Slide 102Slide 103Slide 104Slide 105Slide 106Slide 107Slide 108Slide 109Slide 1101MOS Field-EffectTransistors (MOSFETs)Microelectronic Circuits - Fifth Edition Sedra/Smith 2Copyright  2004 by Oxford University Press, Inc.Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3 m, W = 0.2 to 100 m, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.Microelectronic Circuits - Fifth Edition Sedra/Smith 3Copyright  2004 by Oxford University Press, Inc.Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.Microelectronic Circuits - Fifth Edition Sedra/Smith 4Copyright  2004 by Oxford University Press, Inc.Figure 4.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is determined by vGS. Specifically, the channel conductance is proportional to vGS – Vt’ and thus iD is proportional to (vGS – Vt) vDS. Note that the depletion region is not shown (for simplicity).Microelectronic Circuits - Fifth Edition Sedra/Smith 5Copyright  2004 by Oxford University Press, Inc.Figure 4.4 The iD–vDS characteristics of the MOSFET in Fig. 4.3 when the voltage applied between drain and source, vDS, is kept small. The device operates as a linear resistor whose value is controlled by vGS.Microelectronic Circuits - Fifth Edition Sedra/Smith 6Copyright  2004 by Oxford University Press, Inc.Figure 4.5 Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered shape, and its resistance increases as vDS is increased. Here, vGS is kept constant at a value > Vt.Microelectronic Circuits - Fifth Edition Sedra/Smith 7Copyright  2004 by Oxford University Press, Inc.Figure 4.6 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt.Microelectronic Circuits - Fifth Edition Sedra/Smith 8Copyright  2004 by Oxford University Press, Inc.Figure 4.7 Increasing vDS causes the channel to acquire a tapered shape. Eventually, as vDS reaches vGS – Vt’ the channel is pinched off at the drain end. Increasing vDS above vGS – Vt has little effect (theoretically, no effect) on the channel’s shape.Microelectronic Circuits - Fifth Edition Sedra/Smith 9Copyright  2004 by Oxford University Press, Inc.Figure 4.8 Derivation of the iD–vDS characteristic of the NMOS transistor.Microelectronic Circuits - Fifth Edition Sedra/Smith 10Copyright  2004 by Oxford University Press, Inc.Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the body terminal for the p-channel device.Microelectronic Circuits - Fifth Edition Sedra/Smith 11Copyright  2004 by Oxford University Press, Inc.Figure 4.10 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect of the body on device operation is unimportant.Microelectronic Circuits - Fifth Edition Sedra/Smith 12Copyright  2004 by Oxford University Press, Inc.Figure 4.11 (a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of current flow indicated. (b) The iD–vDS characteristics for a device with k’n (W/L) = 1.0 mA/V2.Microelectronic Circuits - Fifth Edition Sedra/Smith 13Copyright  2004 by Oxford University Press, Inc.Figure 4.12 The iD–vGS characteristic for an enhancement-type NMOS transistor in saturation (Vt = 1 V, k’n W/L = 1.0 mA/V2).Microelectronic Circuits - Fifth Edition Sedra/Smith 14Copyright  2004 by Oxford University Press, Inc.Figure 4.13 Large-signal equivalent-circuit model of an n-channel MOSFET operating in the saturation region.Microelectronic Circuits - Fifth Edition Sedra/Smith 15Copyright  2004 by Oxford University Press, Inc.Figure 4.14 The relative levels of the terminal voltages of the enhancement NMOS transistor for operation in the triode region and in the saturation region.Microelectronic Circuits - Fifth Edition Sedra/Smith 16Copyright  2004 by Oxford University Press, Inc.Figure 4.15 Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length (by DL).Microelectronic Circuits - Fifth Edition Sedra/Smith 17Copyright  2004 by Oxford University Press, Inc.Figure 4.16 Effect of vDS on iD in the saturation region. The MOSFET parameter VA depends on the process technology and, for a given process, is proportional to the channel length L.Microelectronic Circuits - Fifth Edition Sedra/Smith 18Copyright  2004 by Oxford University Press, Inc.Figure 4.17 Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance ro. The output resistance models the linear dependence of iD on vDS and is given by Eq. (4.22).Microelectronic Circuits - Fifth Edition Sedra/Smith 19Copyright  2004 by Oxford University Press, Inc.Figure 4.18 (a) Circuit symbol for