ECE 190 Lecture 10 February 17, 2011 1 V. Kindratenko LC-3 ISA - II Lecture Topics LC-3 data movement instructions LC-3 control instructions LC-3 data path review Lecture materials Textbook § 5.3 - 5.6 Textbook Appendix A.3 Homework HW3 due Wednesday February 23 at 5pm in the ECE 190 drop-off box Machine problem MP2 due March 2, 2011 at 5pm submitted electronically. AnnouncementsECE 190 Lecture 10 February 17, 2011 2 V. Kindratenko LC-3 data movement instructions Overview - Load: move data from memory to register o LD, LDI, LDR o LEA – immediate mode load instruction - Store: o ST, STR, STI - Load/store instruction format opcodedestination or source registeraddress generation bits15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - 4 ways to interpret address generation bits (4 addressing modes) o PC-relevant mode (LD and ST instructions) o Indirect mode (LDI and STI instructions) o Base + offset mode (LDR and STR instructions) o Immediate mode (LEA instruction) Load instruction using base + offset addressing mode (LDR) - Operation: the content of memory at the address computed as the sum of the address stored in the base address register (BaseR) and the sign-extended last 6 bits of the instruction (offset6) is loaded into the destination register (DR) o DR ← mem[BaseR+SEXT(offset6)] o setcc - Encoding: 0opcode1 1 0destination registeroffset615 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0LDRbase address register - Datapath relevant to the execution of this instruction: o Example: 0110 001 010 011101; LDR R1, R2, offsetECE 190 Lecture 10 February 17, 2011 3 V. Kindratenko xABCDx2345R0R1R2R3R4R5R6R7ADD0 1 1 0 0 0 1 0 1 0 0 1 1 1 0 1IR6DR3SEXTIR[5:0]16xABCDMDRMAR1616x1Dx2362x2362BaseR31 0 0N Z P  MAR ← R2 + SEXT(IR[5:0])  MDR ← mem[MAR]  R1 ← MDR - offset6 field is 6-bit wide, thus the offset can be from -32 to +31 Store instruction using base + offset addressing mode (STR) - Operation: value stored in the source register (SR) is transferred to the memory at the address computed as the sum of the address stored in the base address register (BaseR) and the sign-extended last 6 bits of the instruction (offset6) o mem[BaseR+SEXT(offset9)] ← SR - Encoding: 0opcode1 1 1source registeroffset615 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0STRbase address register - Datapath relevant to the execution of this instruction: o Example: 0111 001 010 011101; STR R1, R2, offsetECE 190 Lecture 10 February 17, 2011 4 V. Kindratenko xFEDCx2345R0R1R2R3R4R5R6R7ADD0 1 1 1 0 0 1 0 1 0 0 1 1 1 0 1IR6SR3SEXTIR[5:0]16xFEDCMDRMAR1616x1Dx2362x2362BaseR3  MAR ← R2 + SEXT(IR[5:0])  MDR ← R1  mem[MAR] ← MDR Load instruction using PC relative addressing mode (LD) - Operation: the content of memory at the address computed as the sum of the address stored in PC register and the sign-extended last 9 bits of the instruction (PCoffset9) is loaded into the destination register (DR) o DR ← mem[PC+SEXT(PCoffset9)] o setcc - Encoding: 0opcode0 1 0destination registerPCoffset915 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0LD - Datapath relevant to the execution of this instruction: o Example: 0010 000 110101111; LD R0, offsetECE 190 Lecture 10 February 17, 2011 5 V. Kindratenko 0011001100110011R0R1R2R3R4R5R6R7ADD0 0 1 0 0 0 0 1 1 0 1 0 1 1 1 1IR169DR3SEXTIR[8:0]0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1PC160011001100110011MDRMAR1616x1AFx4018x3FC8x3FC80 0 1N Z P  MAR ← PC + SEXT(IR[8:0])  MDR ← mem[MAR]  R0 ← MDR Store instruction using PC relative addressing mode (ST) - Operation: value stored in the source register (SR) is transferred to the memory at the address computed as the sum of the address stored in PC register and the sign-extended last 9 bits of the instruction (PCoffset9) o mem[PC+SEXT(PCoffset9)] ← SR - Encoding: 0opcode0 1 1source registerPCoffset915 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0ST - Datapath relevant to the execution of this instruction: o Example: 0011 000 110101111; ST R0, offsetECE 190 Lecture 10 February 17, 2011 6 V. Kindratenko 1111111111110000R0R1R2R3R4R5R6R7ADD0 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1IR169SR3SEXTIR[8:0]0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1PC161111111111110000MDRMAR1616x1AFx4018x3FC8x3FC8  MAR ← PC + SEXT(IR[8:0])  MDR ← R0  mem[MAR] ← MDR - PCoffset9 field is 9-bit wide, thus the offset can be from -256 to +255 Load instruction using indirect addressing mode (LDI) - Operation: the content of memory at the address stored in memory at the address computed as the sum of the address stored in PC register and the sign-extended last 9 bits of the instruction (PCoffset9) is loaded into the destination register (DR) o DR ← mem[mem[PC+SEXT(PCoffset9)]] o setcc - Encoding: 1opcode0 1 0destination registerPCoffset915 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0LDI - Datapath relevant to the execution of this instruction:ECE 190 Lecture 10 February 17, 2011 7 V. Kindratenko o Example: 1010 011 111001100; LDI R3, offset xFFFFR0R1R2R3R4R5R6R7ADD1 0 1 0 0 1 1 1 1 1 0 0 1 1 0 0IR169DR3SEXTIR[8:0]0 1 0 0 1 0 1 0 0 0 0 1 1 1 0 0PC16xFFFFMDRMAR1616x1CCx4A1Cx49E8x21101 0 0N Z Px2110x49E8  MAR ← PC + SEXT(IR[8:0])  MDR ← mem[MAR]  MAR ← MDR  MDR ← mem*MAR+  R3 ← MDR Store instruction using indirect addressing mode (STI) - Operation: value from the source register (SR) is transferred to the memory at the address stored in memory at the address computed as the sum of the address stored in PC register and the sign-extended last 9 bits of the instruction (PCoffset9) o mem[mem[PC+SEXT(PCoffset9)]] ← SR - Encoding: 1opcode0 1 1source registerPCoffset915 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0STI - Datapath relevant to the execution of this instruction: o Example: 1011 011 111001100; STI R3, offsetECE 190 Lecture 10 February 17, 2011 8 V. Kindratenko xAAAAR0R1R2R3R4R5R6R7ADD1 0 1 1 0 1 1 1 1 1 0 0 1 1 0 0IR169SR3SEXTIR[8:0]0 1 0 0 1 0 1 0 0 0 0 1 1 1 0 0PC16xAAAAMDRMAR1616x1CCx4A1Cx49E8x2110x2110x49E8  MAR ← PC + SEXT(IR[8:0])  MDR ← mem[MAR]  MAR ← MDR  MDR ← R3  mem*MAR+ ← MDR LC-3 control instructions - Control instructions change the sequence of the instructions that are executed. The achieve this by directly manipulating the value of PC register. - Control instructions supported by LC-3 o JMP - unconditional jump o BR – conditional branch o TRAP – invokes an OS service call o JSR/JSRR – subroutine call o RET – return from subroutine o