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UW-Madison ECE 734 - Superscalar Architecture Design Framework for DSP operations

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Superscalar Architecture Design Framework for DSP operationsThis project would involve development of a superscalar processor optimizer capable of optimizing superscalar architecture for a given benchmark application. This optimizer shall be targeting DSP application specifically. By optimizing, it is implied that the optimizer is going to alter various architectural parameters (Cache Size, Number of Int ALU ets) of the superscalar architecture; so as to tailor it for a given benchmark application. Performance measures will be acquired via simplscalar[1] simulator and its power extension WATTCH[2]. The optimizer would be capable of considering power consumption, performance or a combination of both as its objective function.I have already done some work on this. I have developed an optimizer which implements a heuristic algorithm for superscalar optimization [3]. However, due to its heuristic nature, the algorithm converges to local minimal points. To ensure greater level of design space exploration, it is important to add some level of randomness to the algorithm.Various techniques have already been used in literature [4] [5] [6] [7] for similar architectural optimizations. However, the mentioned optimization techniques considered only a limited set of architectural parameters; resulting in limited design space exploration. This is because; conducting optimizations while considering a large number of superscalar architectural configuration parameters requires very long optimization time. In my approach, simulated annealing would be used and would consider large number of configurations parameters and their corresponding values. The large optimization time is countered by following measures: 1) Using simulated annealing initially to explore a large amount of design space. Terminating the simulated annealing algorithm after a fixed number of simulations.2) Applying the heuristic approach to the final configuration acquired from the simulated annealing approach. Furthermore, other measures can also be taken to make the optimization process more efficient:1) Analyzing optimization results and observing which architectural parameters are optimized sufficiently from the heuristic approach [3]. Not considering those architectural parameters for simulated annealing.2) In the simulated annealing approach, considering architectural parameter values which would be logically relevant for a given operation. For example, DSP algorithms for communication, are not expected to be very intensive interms of their cache requirement….however, they do require a very extensive executioncore. So if optimization is being done for communication related DSP operations, high cache configurations and low execution core configurations will not be considered by simulated annealing for optimization process.3) Varying various parameters associated with the simulated annealing algorithm to ensure converge to a near optimal point with minimum number of simulation cycles.These measures would enable earlier convergence to an optimal point and would hence reduce optimization time. Other improvements to the optimization approach can be effected after analysis of optimization results. Such an optimization tool shall provide designers valuable insight into the performance of their designs. This shall prove particularly useful for software radio applications since the algorithms implemented on such platforms require high processing power inorder to follow realtime constraints; and they also need to have low power consumption for mobile devices. In such applications, this optimization tool can be used by the designers of the architecture to get a superscalar processor configuration which suits the target applications.[1] T. Austin, E. Larson, D. Ernst, “SimpleScalar: An infrastructure for Computer SystemModeling”, IEEE Computers, Feb. 2002, pp. 59-68.[2] D. Brooks, V. Tiwari, M. Martonosi, “Wattch: A Framework for Architectural-LevelPower Analysis and Optimization”, Proceedings of 27th International Symposium onComputer Architecture”, 2000, pp 83-94.[3] F. Sheikh, S. Masud, R. Ahmed, "Superscalar Architecture Design for HighPerformance DSP Operations", Microprocessors and Microsystems, Elsevier, March 2009 (Attached with this email).[4] T.M. Conte, K.M. Menezes, S.W. Sathaye, “A technique to determine power-efficient,high-performance superscalar processors”, Proceedings of the 28th Hawaii International Conference on System Sciences, pp. 324-333, Vol 1, 1995.[5] S.V. Haastregt and P.M.W. Knijnenburg, “Feasibility of Combined Area and Performance Optimization for Superscalar Processors Using Random Search”, Proceedings of Design Automation and Test in Europe, 2007, pp. 1-6.[6] Mauro Olivieri, “A genetic approach to the design space exploration of superscalar microprocessor architectures”, Proceedings of the 2001 IEEE International Symposium on Circuits and Systems, pp. 69-72, Vol 5.[7] V. Zyuban and P. Kogge, “Optimization of high-performance superscalar architecturesfor energy efficiency”, Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, pp.


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