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CMSC 611: AdvancedCMSC 611: AdvancedComputer ArchitectureComputer ArchitectureInstruction Set ArchitectureInstruction Set ArchitectureSome material adapted from Mohamed Younis, UMBC CMSC 611 Spr 2003 course slidesSome material adapted from Hennessy & Patterson / © 2003 Elsevier ScienceLecture OverviewLecture Overview• Last Week– Different performance metrics(response time, throughput, CPU time)– Performance reports, summary and comparison(Experiment reproducibility, arithmetic and weightedarithmetic means)– Widely used benchmark programs(SPEC, Whetstone and Dhrystone)– Example industry metrics(e.g. MIPS, MFLOP, etc.)• This Week– Classifications of instruction set architectures– Different addressing modes– Instruction types, operands and operationsIntroductionIntroduction• To command a computer's hardware, you must speakits language• Instructions: the “words” of a machine's language• Instruction set: its “vocabulary• The MIPS instruction set is used as a case studyinstruction setsoftwarehardwareFigure: Dave PattersonInstruction Set ArchitectureInstruction Set Architecture• Once you learn one machine language, it iseasy to pick up others:– Common fundamental operations– All designer have the same goals: simplify buildinghardware, maximize performance, minimize cost• Goals:– Introduce design alternatives– Present a taxonomy of ISA alternatives• + some qualitative assessment of pros and cons– Present and analyze some instruction setmeasurements– Address the issue of languages and compilers andtheir bearing on instruction set architecture– Show some example ISA’s• A good interface:– Lasts through many implementations (portability,compatibility)– Is used in many different ways (generality)– Provides convenient functionality to higher levels– Permits an efficient implementation at lower levels• Design decisions must take into account:– Technology– Machine organization– Programming languages– Compiler technology– Operating systemsInterfaceimp 1imp 2imp 3useuseuseTimeSlide: Dave PattersonInterface DesignInterface DesignMemory Memory ISAsISAs• Terms– Result = Operand <operation> Operand• Stack– Operate on top stack elements, push resultback on stack• Memory-Memory– Operands (and possibly also result) inmemoryRegisterRegister ISAs ISAs• Accumulator Architecture– Common in early stored-program computers whenhardware was expensive– Machine has only one register (accumulator)involved in all math & logic operations– Accumulator = Accumulator op Memory• Extended Accumulator Architecture (8086)– Dedicated registers for specific operations, e.gstack and array index registers, added• General-Purpose Register Architecture (MIPS)– Register flexibility– Can further divide these into:• Register-memory: allows for one operand to be in memory• Register-register (load-store): all operands in registersISA OperationsISA OperationsFamous ISAFamous ISA• Stack• Memory-Memory• Accumulator Architecture• Extended Accumulator Architecture• General-Purpose Register ArchitectureMachine# general-purposeregistersArchitecture styleYearMotorola 68002Accumulator1974DEC VAX16Register-memory, memory-memory1977Intel 80861Extended accumulator1978Motorola 6800016Register-memory1980Intel 8038632Register-memory1985PowerPC32Load-store1992DEC Alpha32Load-store1992Other types of ArchitectureOther types of Architecture• High-Level-Language Architecture– In the 1960s, systems software was rarely written inhigh-level languages• virtually every commercial operating system before Unixwas written in assembly– Some people blamed the code density on theinstruction set rather than the programminglanguage– A machine design philosophy advocated makingthe hardware more like high-level languages– The effectiveness of high-level languages, memorysize limitation and lack of efficient compilersdoomed this philosophy to a historical footnoteOther types of ArchitectureOther types of Architecture• Reduced Instruction Set Architecture– With the recent development in compiler technologyand expanded memory sizes less programmers areusing assembly level coding– Drives ISA to favor benefit for compilers over easeof manual programming• RISC architecture favors simplified hardwaredesign over rich instruction set– Rely on compilers to perform complex operations• Virtually all new architecture since 1982follows the RISC philosophy:– fixed instruction lengths, load-store operations, andlimited addressing modeCompact CodeCompact Code• Scarce memory or limited transmit time (JVM)• Variable-length instructions (Intel 80x86)– Match instruction length ot operand specification– Minimize code size• Stack machines abandon registers altogether– Stack machines simplify compilers– Lend themselves to a compact instruction encoding– BUT limit compiler optimizationSingle Accumulator (EDSAC 1950)Accumulator + Index Registers(Manchester Mark I, IBM 700 series 1953)Separation of Programming Model from ImplementationHigh-level Language BasedConcept of a Family(B5000 1963)(IBM 360 1964)General Purpose Register MachinesComplex Instruction SetsLoad/Store ArchitectureRISC(Vax, Intel 432 1977-80)(CDC 6600, Cray 1 1963-76)(MIPS,SPARC,IBM RS6000, . . .1987)Slide: Dave PattersonEvolution of Instruction SetsEvolution of Instruction Sets# memory addresses Max. number of operands Examples 0 3 SPARC, MIPS, PowerPC, ALPHA 1 2 Intel 60X86, Motorola 68000 2 2 VAX (also has 3 operands format) 3 3 VAX (also has 2 operands format) Effect of the number of memory operands:TypeAdvantagesDisadvantagesReg-Reg (0,3)- Fixed length instruction encoding- Simple code generation model- Similar execution time (pipeline)- Higher instruction count- Some instructions are short leading to wasteful bit encodingReg-Mem (1,2)- Direct access without loading- Easy instruction encoding- Can restrict # register available for use- Clocks per instr. varies by operand type- Source operands are destroyedMem-Mem (3,3)- No temporary register usage- Compact code- Less potential for compiler optimization- Can create memory access bottleneckRegister-Memory ArchRegister-Memory Arch10010101112840DataAddressMemoryProcessorObject addressed Aligned at byte offsets Misaligned at byte offsets Byte 1,2,3,4,5,6,7 Never Half word 0,2,4,6 1,3,5,7 Word 0,4 1,2,3,5,6,7 Double word 0 1,2,3,4,5,6,7 Memory AddressingMemory Addressing• The address of a word


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