UCF CDA 5106 - Exploring and Exploiting Wire-Level Pipelining in Emerging Technologies

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Exploring and Exploiting Wire-Level Pipelining in Emerging Technologies Michael Thaddeus Niemier University of Notre Dame Dept. of Computer Science and Engineering Notre Dame, IN 46556, USA [email protected] Peter M. Kogge University of Notre Dame Dept. of Computer Science and Engineering Notre Dame, IN 46556, USA [email protected] Abstract Pipelining is a technique that has long since been con- sidered fimdamental by computer architects. However, the worm of nanoelectronics is pushing the idea of pipelining to new and lower levels - particularly the device level. How this qffects circuits and the relationship between their tim- ing, architecture, and design will be studied in the con- text of an inherently se(f-latching nanotechnology termed Quantum Celhdar Automata (QCA). Results indicate that this nanotechnology offers the potential .for "free" multi- threading and "processing-in-wire ". All of this could be accomplished in a technology that could be almost three orders' of magnitude denser than an equivalent design fab- ricated in a process at the end of the CMOS curve, 1. Introduction Pipelining as a technique has been with us every day for almost 40 years. It has been designed into our basic circuits, and governed the way we partition larger logic functions. Technology and market forces have pushed clock speeds to realms where speed of light dictates smaller and smaller amounts of logic per stage. More and more we even rely on transitory storage effects (as in wave pipelining) to push the cycle time to lower and lower limits. This in turn has forced us to introduce new instruction and architectural level ar- tifacts such as vectors, systolic arrays, and more recently multi-threading. As we look toward the near future, we see this trend continuing, especially as we approach the sup- posed end of CMOS at 0.05 microns (50 nanometers). When we look at alternative technologies, we often see this same phenomena of shrinking stage size appearing at the basic technology level. Older technologies such as Charge Coupled Devices and newer self-latching technolo- gies such as Josephson junctions and Rapid Flux Single Quantum devices bring pipelining down to the device level. To date, the unique application niches and difficult imple- mentation environments of such technologies has discour- aged researchers from seriously considering their effects on design. However, it may be time to reconsider the inter- action between timing, architecture, and design. The driv= ing force is the rapidly expanding world of nanoelectronics, where devices as small as a molecule may be feasible. This paper is the outgrowth of design work with one such technology just recently demonstrated, but for which there is strong evidence that room temperature systems made from 2 nm devices may only be a few years away. This technology, termed Quantum Cellular Automata (QCA), is at its base, self-latching, where information is stored at each device by the positions of single electrons, and logic func- tions are performed not by electron flow but by Coulombic interactions. The result is a technology where even the in- terconnect is made out of the same self-latching devices as the logic functions, bringing "pipelining" down well below the level of even a simple logic gate. Thus, while focused on QCAs, our goal in this paper is to reopen the topic of pipelining at an extremely low level, and begin to explore how what today are high level techniques - such as multi-threading - may in fact in the future become part and parcel of micro-organizational levels of design. To support this, Sec. 2 first reviews the QCA technology to in- troduce where this ultra low level pipelining originates. Sec. 3 discusses the concept of a "clock" in such a context. Sec. 4 provides a motivational example of what the technology may mean in terms of comparison at the dataflow level to the CMOS roadmap. Sec. 5 then explores what is perhaps a more fundamental issue - what does such a technology mean to the design of the state machines that control such data flows? Sec. 6 introduces a canonical approach to their design and gives examples. Sec. 7 will describe a primitive architecture. Sec. 8 concludes with a discussion of what are the most important near term research issues. 2. The QCA Device, Circuits, and Experiments 2.1. The Device A high-level diagram of a four-dot QCA cell appears in Fig. 1. It consists of four quantum dots that are positioned 166 1063-6897/01 $10.00 © 2001 IEEEto form a square. (Note: Future QCA cells have the po- tential to shrink dots to regions within specially designed molecules). Exactly two mobile electrons are loaded in the cell and can move to different quantum dots in the QCA cell by means of electron tunneling. Coulombic repulsion will cause the electrons to occupy only the comers of the QCA cell resulting in two specific polarizations (see Fig. 1 ). These polarizations represent the places where the electrons are as far apart from one another as possible (which hence minimizes the Coulombic repulsion between them) without escaping the confines of the cell. Electron tunneling is as- sumed to be completely controllable by potential barriers that can be raised and lowered between adjacent QCA cells by means of capacitive plates [14]. P=+I P=-I (Binar y 1 ) (Binar y 0) Figure 1. QCA cell polarizations. 2.2. Circuits The fundamental QCA logical circuit is the three-input majority gate (Fig. 2) [14]. Computation is performed by driving the device cell (cell 4 in the figure) to its lowest en- ergy state. This occurs when it assumes the polarization of the majority of the three input cells. The device cell will always assume the majority polarization because in this po- larization, electron repulsion between the electrons in the three input cells and the device cell will be at a minimum. Cell 4 (device cell) Cell 1 (input) ~ ]: .';,I / Cell 5 (output) Cell 2 (input) ~1-- Cell 3 (input) Figure 2. The fundamental QCA logical de- vice. Fig. 3 illustrates a representation of what is called a "90- degree wire". Assume that the middle cell in Fig. 3 was originally in a polarization opposite of that of the first cell. Thus, if the first cell represents an input cell, the electrons would move as illustrated by the arrows in the figure to take on a


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