Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS Rajani Kuchipudi and Hamid Mahmoodi School of Engineering, San Francisco State University, San Francisco, CA {rajanik, mahmoodi}@sfsu.edu Abstract Straining of silicon improves mobility of carriers resulting in speed enhancement for transistors in CMOS technology. Traditionally, silicon straining is applied in a similar ad-hoc manner to the whole die including logic and memory. Speed enhancement achieved for both NMOS and PMOS devices is desirable in logic circuits for performance enhancement because both PMOS and NMOS devices lie in critical delay paths. In SRAM cells however PMOS devices are not in the delay path and hence made small to minimize cell area and improve the write stability of the cell. Hence, speed enhancement of PMOS does not result in any reduction in cell access time and in fact it degrades the cell write ability. Hence, optimal method and amount of silicon straining for logic and memory should be different. In this paper, we propose an optimal straining solution for both logic and memory. Based on simulation results in a predictive 45nm process technology, the proposed straining solution enhances circuit performance by 15.6% in SRAM and 39.3% in Logic while satisfying stability requirements. We also propose a co-design optimization methodology that allows optimizing circuit parameters (such as transistor sizing and supply voltage) and process parameters (in this case amount of silicon straining) at the same time for both low power and high performance targets. We found that co-design of supply voltage and silicon straining is very helpful for both low power and high performance targets, whereas co-design of sizing and silicon straining dose not provide any considerable improvements. Our results show that by co-design of supply voltage and silicon straining, power reduction of 38% and 49% is achieved in SRAM and logic, respectively. We also expanded our co-design approach for joint optimization of various circuit and device parameters such as supply voltage, straining, and threshold voltage. The results show that the co-design can reduce leakage by 80% and improve performance by 50%. The developed optimization methodology thus provides a device and circuit co-design framework which is essential as the technology continues to scale to nano-scale regimes. 1. Introduction The semiconductor industry has recently adopted the concept of silicon straining to enhance the circuit performance. This technology takes advantage of the natural tendency for atoms inside compounds to align with one another. When silicon is deposited on top of a substrate whose atoms are spaced farther apart, the atoms in silicon stretch to align with the atoms beneath, stretching or straining the silicon. In the strained silicon, electrons experience less resistance and flow faster, leading to faster chips without having to shrink the size of transistors [1,2]. Thus, device improvement with strain engineering is nothing but enhancing mobility. So far, silicon straining is applied to both NMOS and PMOS in an ad-hoc manner regardless of the specific circuits. We show that such an approach does not necessarily provide the best of straining technology to all types of circuits. Speed enhancement achieved for both NMOS and PMOS devices is desirable in static CMOS logic circuits for performance enhancement because both PMOS and NMOS devices exist in critical paths. In SRAM however PMOS devices are not in the read delay path and hence designed to be small in order to reduce the cell area and improve the cell write stability. If PMOS strength increases too much by straining, it will degrade SRAM cell write stability without any improvement in the access time. Hence optimal straining of NMOS and PMOS devices is expected to be different for logic circuits and memory cells. Moreover, traditionally, circuit designer have not been considering change of straining since it is a process parameter that seems to be out of control of circuit designers. However, combined circuit and process optimization (device-circuit co-design) can result in a much more optimal design. Thus, a circuit-device co-optimization framework is necessary for future designs. In this paper, we first propose an optimal straining solution for both logic and memory. We then propose an optimization methodology that allows optimizing circuit parameters (such as supply voltage and transistor sizing) and process parameters (in this case amount of silicon straining) at the same time for both low power and high performance targets. Our results show that co-design of supply voltage and silicon straining is very effective for low power designs, achieving a power reduction of 38% in SRAM and 49% in logic circuits. However, co-design of sizing and silicon straining doe not show any considerable improvements. We also expand our co-design approach for joint optimization of supply voltage, straining, and threshold voltage. The results show that through such a co-design, leakage power can be reduced by 80% and performance can be improved by 50% in SRAM. The remainder of this paper is organized as follows. In section 2, impact of silicon straining on transistor characteristics is discussed. In section 3, simulation results obtained from straining SRAM cell and ring oscillator are analyzed. In section 5, optimal straining solutions for memory and logic circuits are discussed. In section 6, different circuit-device optimization techniques proposed for high-performance and low-power applications are discussed. Finally the conclusion of the paper appears in section 7. 2. Impact of Silicon Straining on Transistor Characteristics In this work, the effect of silicon straining is modeled by multiplying the mobility parameter (U0) in spice model card Proceedings of the 8th International Symposium on Quality Electronic Design (ISQED'07)0-7695-2795-7/07 $20.00 © 2007Authorized licensed use limited to: San Francisco State Univ. Downloaded on December 10, 2008 at 22:41 from IEEE Xplore. Restrictions apply.by a new parameter called Kn for NMOS and Kp for PMOS. We use a 45nm predictive technology model [5]. The effect of varying Kn and Kp on Ids/Vgs characteristics of NMOS and PMOS devices is shown in Fig 1. Ioff and Ion both increase by applying straining. By silicon straining, Ioff increases at a faster rate than Ion. Hence, the Ion/Ioff ratio goes down due to silicon straining