Introduction to Computers and ProgrammingLecture 7 •–––computerprocessor memory ALUCU10101101…01111000InputbusProf. I. K. LundqvistReading: B pp. 505-507, Machine language handout Sept 16 2003Recap – Computer Architecture Computer Organization The von Neumann architecture Same storage device for both instructions and data The von Neumann Bottleneck devices Reg Reg Output•––•–––CPU MemoryDVDHard drive Networkdescribed in Appendix C Recap – Computer Architecture Device Controllers Memory mapped I/O Direct Memory Access (DMA) Instruction Set Data transfer operations Arithmetic / logic operations Control flow instructions Video controller controller USB controller controller Outside world controller The architecture of the machine Hard drive Hard drive Hard drive Program counterInstruction registerCPU Main memoryAddress Cells00010203FFBusRegisters012FArithmetic / Logic Unit Control Unit. . . . .. . . . .Program Execution “The machine cycle” The composition of an instruction for the machine in Appendix C ExecuteDecodeFetch1. Fetch next instructionfrom memory (as indicatedby the program counter)then increment theprogram counter.2. Decode the bit pattern inthe instruction register.3. Execute the action requestedby the instruction in theinstruction register.3 5 A 70011 0101 1010 0111Op-code Operand16-bit pattern4-digit hexadecimal formStored Program Performing the fetch step of the machine cycle I Program counterInstruction registerA2CPU Main memoryAddress CellsA0 15A1 6CA2 16A3 6DA4 50A5 56A6 30A7 6EA8 C0A9 00BusRegisters012FProgram counter contains address of first instructions.Program isstored in mainmemorybeginning ataddress A0.. . . . .Program counterInstruction registerA0156CCPU Main memoryAddress CellsA0 15A1 6CA2 16A3 6D1. At the beginning of the fetch step the instruction starting at address A0 is retrievedfrom memory and placed in the instruction register.BusPerforming the fetch step of the machine cycle II Decoding the instruction 35A7 Program counterInstruction registerA2156CCPU Main memoryAddress CellsA0 15A1 6CA2 16A3 6D2. Then the program counter is incremented so that it points to the next instruction.Bus3 5 A 7Instruction[[Op-code 3 meansto store the contentsof a register in a memory cell.This part of the operandidentifies the registerwhose contents are to bestored.This part of the operandidentifies the address of thememory cell that is to receive data.Mnemonics• It is hard to remember many numbers• Use words associated with the numbersjmpLEjmpLEreg<=R0,addrjmpjmp addrrotate rightror reg, numbitwise XORxor reg, reg, reghaltjmpEQjmpEQreg=R0,adrbitwise ANDand reg, reg, regbitwise ORor reg, reg, regfloatingpointadditionaddf reg, reg, regintegeradditionaddi reg, reg, regmovemove reg1, reg2indirectstorestore reg, [reg]direct storestore reg, [addr]indirectloadload reg, [reg]direct loadload reg, [addr]immediateloadload reg, addrorgdb3 5 A 7Instruction[[StoreR5[0xA7]store R5, [0xA7] <=> 35A7Assembly Language I • immediate load load reg,numberload reg,label• direct load load reg,[adr]• indirect load load reg1,[reg2]• direct store store reg,[adr]• indirect store store reg1,[reg2]• unconditional jumpjmp adr• originorg adr• data bytedb dataitemjmp Startorg 0x30;Start:load R0, 0x10;load R1, [R0];load R2, [new_number];Store R1,[new_number];Store R2, [R0];halt;org 0x20;new_number : db 10dorg 0x10;old_number : db 25d;Program that switches the contents in memory location 0x20 and 0x10CQ I Assembly II •or reg1,reg2,reg3•and reg1,reg2,reg3•xor reg1,reg2,reg31. Both Contain 0 2. 0xfe contains 0,0xff contains 04 3. 0xfe contains 0, 0xff contains 05 4. I don’t know bitwise or bitwise and bitwise exclusive orload R1, 00100110b;load R2, 11111111b;load R0, 00000000b;and R3,R1,R2;and R4,R1,R0;or R5,R1, R2;or R6, R1, R0;xor R7,R1, R2;halt;Program to demonstrate the basic bit-wise constructsCQ II 1. 1001 2. 0000 3. 0110 4. I don’t
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