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Berkeley PHYSICS 111 - JFET Circuits II

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University of California at Berkeley Last Revision: August 2010 Page 1 of 11 ©2010 Copyrighted by the Regents of the University of California. All rights reserved. Physics 111 Laboratory Basic Semiconductor Circuits (BSC) Lab 5 JFET Circuits II ©2010 by the Regents of the University of California. All rights reserved. References: Hayes & Horowitz Chapter 3 Horowitz & Hill Chapter 3 In this lab you will investigate some more sophisticated JFET circuits, such as voltage amplifiers, differential amplifiers, attenuators, and modulators. Before coming to class complete this list of tasks: • Completely read the Lab Write-up • Answer the pre-lab questions utilizing the references and the write-up • Perform any circuit calculations or anything that can be done outside of lab. • Plan out how to perform Lab tasks. Pre-lab questions: 1. Explain in detail how a signal applied to the gate of one transistor in a differential amplifier can produce an output on the drain of the other transistor. 2. What are parasitic oscillations? How do you minimize them? Do not forward bias the JFET gates. Forward gate currents larger than 50mA will burn out the JFETs Use a Heat Sink on the JFETs. The Laboratory Staff will not help debug any circuit whose power sup-plies have not been properly decoup-led!Physics 111 BSC Laboratory Lab 5 JFET Circuits II RR+VVVinoutDSBackground Voltage Amplifiers Adding a drain resistor RD to a source-follower turns it into a voltage ampli-fier, as shown to the right. The equivalent small signal cir-cuit for the amplifier is shown to the left and is most easily un-derstood by remembering that the current in a source follower is given bLast Revision: August 2010 Page 2 of 11 ©2010 Copyrighted by the Regents of the University of California. All rights reserved. y ivRrSS=+in, where rs = 1/gm. Since this current is unchanged by the addition of the drain resistor, the output voltage will be vRiRRDSout=− =−rvDSin+. e gain of the amplifier is Thus th GRRr RRDSsDS=−+≈−() , (1) where the last equality assumes that the transconduc-put impedance in the follower circuit, it is not low. tance is high. As with the source follower, the input current is given by the gate leakage current, so the amplifier’s input impedance is extremely high. The output impedance of the amplifier equals the drain resistance RD, and unlike the outGDS0VRSvinvoutrSRD+V Differential Amplifiers Differential amplifiers have two inputs, V+ and V−, and one or two outputs. In an ideal differential amplifier, the amp’s output de-pends solely on the difference between the two inputs, VΔ = (V+ − V−)/2. Thus Vout = GVΔ. Unfortunately, the out-put of any real differential amplifier also depends weakly on the average of the two inputs. This av-erage, VC = (V+ + V−)/2, is called the common mode of the amp. VoutV-V+V =G( - )/2outV+V- Differential amplifiers are one of the most common building blocks in analog circuit design. The front end of every op amp, for example, consists of a differential amplifier. Differential amplifiers are used whenever a desired signal is the difference between two signals, particularly when this differ-ence is masked by common mode noise. A typical example is an electrocardiogram. The heart gener-ates electrical signals, which can be detected by electrodes placed against the skin, but the signal from a single electrode would be swamped by background pickup. As you know from touching the oscilloscope input, the body is an excellent antenna for noise in frequencies ranging from 60Hz to 100MHz. Fortunately these undesired signals are nearly equal everywhere on the body. By using two pickups, placed so that the signal from the heart has opposite sign, and amplifying them in a differential amplifier, the desired signal from the heart can be preferentially amplified over the un-wanted noise. Differential amplifiers are constructed from a matched pair of transistors as shown to the lower left.Physics 111 BSC Laboratory Lab 5 JFET Circuits II The drain of either transistor can be used as the output; in some cases both JFET drains are used to provide a differential output.1 The amplifier’s low common mode gain is immediately apparent by redrawing the circuit below: Last Revision: August 2010 Page 3 of 11 ©2010 Copyrighted by the Regents of the University of California. All rights reserved. ode gain will be given by Eq. (1): R+VRRDRDS1RSVV+outV- +RR2R DRDS1 R S V out +V+V2R1VCVC Since the transistors are identical, and since a commonmode drive impresses the same signal on both transis-tors, both halves of the circuit will behave identically. Thus the common mRRR rDSS21++. (Note that the common resistor R1 splits into two parallel resistors of twice the original value.) In practice, the common resistor R1 is always made much greater than the source resistors, so the gain reduces to RD/2R1. As R1 is also made much larger than the drain resistor RD, common mode signals are strongly attenuated. The response of the two transistors to a small differen-tial signal VΔ, on the other hand, will be equal and oppo-site. The net current flow Io through, and voltage drop across, the common resistor will not change. Consequently the common resistor can be replaced with a voltage source of strength R1Io: Equation 1 yields the differential gain RRrDSS+. If RD is chosen to be much greater than the source resistors, the differential gain can be quite large. The total Vout is the sum of Vout–C and Vout−Δ. R+V RR I DRDS1 0 R S V outΔ +VD-VD What happens if a signal is applied to just one input and the other is grounded? The signal can be decomposed into its common and differential components. For a signal applied solely to the V+ input, the common mode signal will be VC = V+/2 and the differential signal will be VΔ = V+/2. (Note how V− = VC − VΔ = 0.) The gain for this single input will be half the differential gain: RD/2(RS + rs). JFET Linearization The linear-regime resistance RDS between a JFET’s drain and source is given by 1 Two outputs of opposite phase.Physics 111 BSC Laboratory Lab 5 JFET Circuits II ()⎥⎦⎤⎢⎣⎡−−=221DSGSDSVVVkRP, rasitic os-tions. . either accentuate or suppress the os-illations. where k is a parameter that depends on the individual JFET, VP is the voltage where the JFET first conducts (the pinch-off, or threshold voltage), and VDS is the


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