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Analysis and Design of High- Speed Interconnects

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Analysis and Design of High-Speed InterconnectsCheng-Kok KohSchool of Electrical and Computer EngineeringPurdue [email protected]://www.ece.purdue.edu/~chengkokOutline Interconnect challenges Inductance extraction Twisted-bundle layout structure Future directionsInterconnect challenges Interconnect delay Interconnect delay dominates gate delay Delay variation Capacitive coupling Inductive coupling Signal integrity Capacitive and inductive couplings Decreasing supply voltageInductance formulas Parallel filaments Geometry Mean Distance (GMD) Pre-computed tables Exact formula for self and mutual inductances C. Hoer and C. Love, 1965 Numerically unstable]1)1[ln(22222ldlddldlM ++−++=πµNumerical instability of Hoer and Love’s formula05e-081e-071.5e-072e-072.5e-073e-070 10000 20000 30000 40000 50000 60000 70000 80000 90000 100000Inductance (H)Wire Length (um)05e-091e-081.5e-082e-082.5e-083e-083.5e-084e-080 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000Inductance (H)Wire Length (um)Self-inductance: Mutual-inductance:New exact formula: Virtual wires0,0,0P0,1,0P1,1,0P1,0,0p1,0,1P1,1,1P0,1,1P0,0,1P0,0,0q0,1,0q1,1,0q1,0,0q1,0,1q1,1,1q0,1,1q0,0,1qyzxMutual inductance111000101010101010210,,,,,11100)1(811kjikjiqpkkjjiikkjjiiLATWTWM∑=++++++−= Mutual inductance in terms of self-inductances of virtual wires  Numerically stable exact closed-form formula for self-inductance exists [Ruehli, IBM’72, Wu-Kuo-Chang, Tmicrowave’92]Numerical results Mutual inductance Cross-section: 0.5 µm X 1 µm Separation: 1.5 µm  Length: variesOur formula05e-091e-081.5e-082e-082.5e-083e-083.5e-084e-080 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000Inductance (H)Wire Length (um)C. Hoer and C. Love’s formula-1 e -0 801e-082e-083e-084e-085e-086e-087e-088e-089e-080 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000Inductance (H)Wire Length (um)Modified FastHenry05e-081e-071.5e-072e-072.5e-070 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000Inductance (H)Wire Length (um)05e-091e-081.5e-082e-082.5e-083e-083.5e-084e-080 200 400 600 800 1000 1200 1400 1600 1800 2000Inductance (H)Wire Length (um)Self-inductance: Mutual-inductance:Skin Effect Example10101005.1e-115.2e-115.3e-115.4e-115.5e-115.6e-115.7e-115.8e-111 100 10000 1e+06 1e+08 1e+10 1e+12 1e+14 1e+16 1e+18Inductance (H)Frequency (Hz)Our toolFasthHenryMutual InductanceTwisted bundle layout structure Motivation and construction Twisted-pair Loop inductance based Synthesis of ground line and signal lines simultaneously Re-ordering of wires to reduce inductive coupling Verification PEEC based Consider P/G mesh12221/)(2221ISdBSdBMssrrrr⋅+⋅=∫∫∫∫12121/)(2121ISdBSdBssrrrr⋅−⋅=∫∫∫∫0=Zero coupling inductanceloop11loop12loop2s21s22Twisted-pair structureMultiple-signal busTwisted groupnormal groupgroundsignal 1signal 2signal 3Current loops due to signal 2loop21loop22loop23loop24groundsignal 216-bit twisted-bundle busTwistedgroupnormal groupTwistedgroupnormal groupStick diagram of the layoutNOT drawn to scaleNormal structureExperiment setup Wire length: 1mm, 2mm, 4mm driver: 160X, receiver: 40X 1.5V Vdd PEEC modelPower/Ground GridP/G Pitch: M6, 150µm; M5 50µmP/G Width: M6 60µm; M5 10µmP/G Pad Pitch: 300µmSignal Pitch: 1µmSignal Width: 0.5µmWire Thickness: 1µmNoise Comparison (1mm, 1GHz)0.10.150.20.250.30.350.40.451 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16Max Noise (V)Signal IndextwistednormalFuture Directions Inductance extraction: Double inversion in frequency-dependent inductance extraction too costly Substrate conductivity Fast simulation and analysis Reduced order modeling Exploit the sparsity of L-1 Interconnect optimization Signal-to-power ratio Shield width, signal width,


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