1CS365 1A Second Datapath Example YH16Lecture 09Prof. Yih HuangCS365 2A 16-Bit Architecture: YH16 A “word” is 16 bit wide 32 general purpose registers, 16 bits each Like MIPS, R0 is hardwired zero. 16 bit PC 16 bit ALU Memory space: 216words.2CS365 3Instruction Format Irs ← rs − rtsub001000rs ← rs XOR rtxor000011rs ← 1 if rs<rt, or 0 otherwise slt001100rs ← rs OR rtor000010rs ← rs AND rtand000001rs ← rs + rtadd000000meaningnameopcodeopcode6 bitsrs5 bits5 bitsrt04591015CS365 4Instruction Format IIopcode6 bitsrs5 bits5 bitsrtImmediate16 bitsrt ← rs − Immd16subi011000rt ← rs XOR Immd16xori010011rt ← rs OR Immd16ori010010rt ← rs AND Immd16andi010001rt ← rs + Immd16addi010000meaningnameopcode3CS365 5Memory Reference InstructionsIIIIIIformatMem[rs+Immd16] ← rtsti100011Mem[rs] ← rtst100010rt ← Mem[rs+Immd16]ldi100001rt ← Mem[rs]ld100000meaningnameopcodeCS365 6Branch InstructionsPC ← rs, if rt = 0Ibf110001PC ← rs, if rt ≠ 0Ibt110000IIIIformatPC ← PC+Immd16, if rs ≠ rtbne110101PC ← PC+Immd16, if rs = rtbeq110100meaningnameopcode bt: branch when true bf: branch when false Unconditional branches ?4CS365 7Exercise Create a program that performsMem[F0F2] = Mem[F0F0] + Mem[F0F1]100010011002100310041005100610071008100AAssembly codeMachine codeCS365 8Exercise Create a program that jumps to location ABCD when Mem[2000] is zero. 100010011002100310041005100610071008100AAssembly codeMachine code5CS365 9Processor Memory InterfaceaddrportdataportAddrbusRW0: Read1: WriteCPUMemoryopAPCCBDatabusMDxMAxMDRIRC00011001CS365 10Data PathRegisterFileABALUCCPCMDRMDR1rtRd#2Rd#1Wr#rs rt0 1Z0 10rsDCUseR0UseRtPC01000110111x2x01101100RFxALUop6CS365 11 Can’t write to PC if PCw==0. When PCw==1write PC if UseZ==00write PC if UseZ==01 and Z==1write PC if UseZ==10 and Z==0 Input to PC determined by PCxPCCA00 01ZUseZZ10PCw1PCxWriteenable01CS365 12Control Singals opcode ≡ IR[15:10] rs ≡ IR[9:5] rt ≡ IR[4:0]SLTSUBADDXORORAND110010110011001000010000 ALUop (4 bits)7CS365 13 Multiplexer controls: 1x (mux for the 1stinput of ALU) , 2x (mux for the 2ndinput of ALU), RFx (mux for register file write), PCx (mux for PC)MAx (mux for memory address) MDx (mux for memory data)CS365 14 Write enable controls: Aw, Bw, Cw, PCw, RFw, IRw, MDRw, RW UseZ: whether to use the Zero output from ALU to affect PC writes. UseR0: whether the first read register # is rsor 0. UseRt: whether the write register # is rs or rt.8CS365 15Discussion Notice the lack of Zw (enable-write-to-Z) Z is written in all cycles. This creates constraints in timing. Example, to see A==BThere is only one cycle where Z reflects the result of A−B.That cycle follows the cycle of A-B. You must take into account these constraints when designing cycle by cycle activities of instructions.CS365 16Exercise Give the control signals to fetch the next instruction and increase PC at the same time.IR ← Mem[PC]C ← PC + 1ALUWrite EnablesA BPCRFIRMDRCRWMultiplexer Controls1 2 RFPCMAMDUseZR0Rt9CS365 17Exercise Give the control signals to carry out the following tasks in one cycle:C ← PC – CA ← R0Rt ← PCALUWrite EnablesA BPCRFIRMDRCRWMultiplexer Controls1 2 RFPCMAMDUseZR0RtCS365 18ADD Cycle 0: IR ← Mem[PC]C ← PC + 1 Cycle 1: PC ← CA ← Reg[rs]B ← Reg[rt] Cycle 2:C ← A + B Cycle 3:Reg[rs] ← CInstructions and, or, xor, sub, slt are similar.10CS365 19Hints This is not a programming exercise. Activities in each cycle must be doable with the datapath without conflicts in resources. Parallel activities are not mandatory, that is, one-cycle-one-action is not wrong. In practice, parallel activities are highly desired in order reduce the numbers of cycles per instruction.CS365 20Exercise Give the control signals to execute ADD. ALUWrite EnablesA BPCRFIRMDRCRWMultiplexer Controls1 2 RFPCMAMDUseZR0Rt11CS365 21ADDI Cycle 0: IR ← Mem[PC]C ← PC + 1 Cycle 1: PC ← CA ← Reg[rs]MDR ← Mem[C] Cycle 2:C ← A + MDR Cycle 3:Reg[rt] ← CC ← PC + 1 Cycle 4:PC ← Candi, ori, xori, subi are similarCS365 22Exercise Give the control signals to execute ADDI. ALUWrite EnablesA BPCRFIRMDRCRWMultiplexer Controls1 2 RFPCMAMDUseZR0Rt12CS365 23LD (Load) Cycle 0: IR ← Mem[PC]C ← PC + 1 Cycle 1: A ← Reg[rs]PC ← C Cycle 2:MDR ← Mem[A] Cycle 3:Reg[rt] ← MDRCS365 24Exercise: ST (Store)13CS365 25LDI (Load with Immd) Cycle 0: IR ← Mem[PC]C ← PC + 1 Cycle 1: A ← Reg[rs]MDR ← Mem[C]PC ← C Cycle 2:C ← A + MDR Cycle 3:C ← PC + 1MDR ← Mem[C] Cycle 4:Reg[rt] ← MDRPC ← CCS365 26Exercise Give the cycle by cycle actions of STI14CS365 27Exercise Give the control signals to execute STI. ALUWrite EnablesA BPCRFIRMDRCRWMultiplexer Controls1 2 RFPCMAMDUseZR0RtCS365 28BT (branch when true) Cycle 0: IR ← Mem[PC]C ← PC + 1 Cycle 1: PC ← CA ← Reg[0]B ← Reg[rt] Cycle 2:Z ← (A==B)A ← Reg[rs] Cycle 3: PC ← A, if Z15CS365 29BEQ Cycle 0: IR ← Memory[PC]C ← PC + 1 Cycle 1: PC ← CMDR ← Mem[C]A ← Reg[rs]B ← Reg[rt] Cycle 2: C ← PC + 1 Cycle 3: PC ← C Cycle 4:C ← PC + MDR Cycle 5:Z ← (A==B) Cycle 6: PC ← C, if ZCS365 30Exercises Give the control signals of BEQ cycle 6 Give the control signals of BT cycle 3. ALUWrite EnablesA BPCRFIRMDRCRWMultiplexer Controls1 2 RFPCMAMDUseZR0RtALUWrite EnablesA BPCRFIRMDRCRWMultiplexer Controls1 2 RFPCMAMDUseZR0Rt16CS365 31The Control Unit The control unit is responsible for generating control signals so that the datapath carries out right actions at right times. We use a 3-bit register S to keep track of the present cycle in executing the current instruction (2ndcycle of add, 5thof ldi, …)S is just three D flip-flops.CS365 32Generating Control SignalsThe conditions when PCw is true:Cycle 1 of all instructionsCycle 3 of bt, bfCycle 4 of addi, andi, ori, xori, subiCycle 4 of ldi, stiCycle 6 of beq, bne17CS365 33Boolean expression to generate PCw:S2S1S0+ S2S1S0 ( I15I14I13I12I11I10+ I15I14I13I12I11I10 ) +S2S1S0 ( I15I14I13I12I11I10 +I15I14I13I12I11I10 +I15I14I13I12I11I10 +I15I14I13I12I11I10 +I15I14I13I12I11I10 ) +S2S1S0(