Switched Capacitor Circuits IIDr. Paul HaslerGeorgia Institute of TechnologyBasic Switch-Cap Integratorφ1GNDV1[n]Vout[n]φ2GNDC2C1Vout[n] = Vout[n-1] - (C1/C2) V1[n]Vout(z)1 - z-1V1(z)= H(z) = - (C1/C2)1H(jω) = - (C1/C2)1 - e-jωT1~ - (C1/C2) / jωTassumes ωT << 1; thereforewe need to sample much higher (factor of 10 to 20)over frequencies of interest.Switch-Cap Implementationφ1GNDV1[n]Vout[n]φ2GNDC2C1φ1GNDV1[n]Vout[n]φ2GNDC2C1Switch-Cap Implementationφ1GNDV1[n]Vout[n]φ2GNDC2C1Transistor switches result in: • Parasitic capacitances• Charge / clock feedthroughSwitch-Cap Implementationφ1GNDV1[n]Vout[n]φ2GNDC2C1φ1GNDV1[n]Vout[n]φ2GNDC2C1GNDCp1GNDCp2GNDCp3GNDCp4Cp5GNDGNDCp0Now adding Parasitic capacitors:Switch-Cap Implementationφ1GNDV1[n]Vout[n]φ2GNDC2C1GNDCp1GNDCp2GNDCp3GNDCp4Cp5GNDGNDCp0Fortunately, many of these capacitors have minimal effect on the circuit• Parasitic capacitances to a voltage source can be neglected• Parasitic capacitances to a “virtual” AC GND can be neglected(the effect of the capacitance is divided by the open-loop gain)Switch-Cap Implementationφ1GNDV1[n]Vout[n]φ2GNDC2C1GNDCp1GNDCp2We still have parasitic capacitances effecting our resultWe can either make large to swamp out parasitic capacitors, or use a stray insensitive designSwitch-Cap Integratorφ1GNDV1[n]V2 [n]φ1φ2Vout[n]φ2GNDC2C1• We will step through all four phases, to get the proper result.Switch-Cap IntegratorGNDV1[n-1]V2 [n-1]Vout[n-1]GNDC2C1• This case is important to understand our starting pointcharge is stored on a capacitor ; therefore we need to know the initial state(4), [n-1] cycleQ = -C2Vout[n-1]Voltage = 0V(Voltage remains held)Switch-Cap IntegratorGNDV1[n]V2 [n]Vout[n-1]GNDC2C1• Charge up the capacitor with voltage V1[n] (1), [n] cycle: φ1Q = -C2Vout[n-1](Output unchanged)V1[n]Switch-Cap IntegratorGNDV1[n]V2 [n]Vout[n-1]GNDC2C1• We remove the capacitor from the first voltage. • The voltage is stored across the capacitor(2), [n] cycleQ = -C2Vout[n-1](Output unchanged)V1[n]Q1= C1V1[n]Q1= -C1V1[n]Switch-Cap IntegratorGNDV1[n]V2 [n]Vout[n-1] + (C1/C2) (V2[n]- V1[n])GNDC2C1• We connect the capacitor to the charge summing node• The charge initially stored on the capacitor as well as the resulting charge from the second input (V2 [n]) contributes to the total charge(3), [n] cycle: φ2Q = -C2Vout[n-1]+ C1V1[n]- C1V2[n]Switch-Cap IntegratorGNDV1[n]V2 [n]Vout[n] = Vout[n-1] + (C1/C2) (V2[n]- V1[n])GNDC2C1• We disconnect the capacitor from the charge summing node, and return to our initial case(4), [n] cycle(Output unchanged)Q = -C2Vout[n-1]+ C1(V1[n]-V2[n])Vout[n] = Vout[n-1] + (C1/C2) (V2[n]- V1[n])Switch-Cap Integratorφ1GNDV1[n]V2 [n]φ1φ2Vout[n]Cφ2GNDBy switching which input is first, we can digitally invert the signalA[n]V1[n]V2 [n]Vout[n]A[n]φ1φ2Differential Switch-Cap Circuitφ1φ1φ2Vout+[n]φ2Vout-[n]Vin+[n]Vin-[n]Why?C2C1C2Differential Switch-Cap Circuitφ1φ1φ2Vout+[n]φ2Vout-[n]Vin+[n]Vin-[n]Why? Higher PSRR, lower harmonic Distortion, lower noiseCost?C2C1C2Differential Switch-Cap Circuitφ1φ1φ2Vout+[n]φ2Vout-[n]Vin+[n]Vin-[n]Why? Higher PSRR, lower harmonic Distortion, lower noiseCost? Larger Op-Amp, more powerC2C1C2Vin[n] = Vin+[n] - Vin-[n]Vout[n] = Vout+[n] - Vout-[n](assume balanced output)Differential Switch-Cap CircuitVout+[n-1]Vout-[n-1]Vin+[n-1]Vin-[n-1]C2C1C2• This case is important to understand our starting pointcharge is stored on a capacitor ; therefore we need to know the initial state(4), [n-1] cycleQ = -C2Vout[n-1]/2Voltage = 0V(Voltage remains held)Q = C2Vout[n-1]/2Differential Switch-Cap CircuitVout+[n-1]Vout-[n-1]Vin+[n]Vin-[n]C2C1C2• Charge up the capacitor with voltage Vin[n] (1), [n] cycle: φ1(Output unchanged)Vin[n]Q = -C2Vout[n-1]/2Q = C2Vout[n-1]/2Differential Switch-Cap CircuitVout+[n-1]Vout-[n-1]Vin+[n]Vin-[n]C2C1C2• We remove the capacitor from the first voltage. • The voltage is stored across the capacitor(2), [n] cycle(Output unchanged)Vin[n]Q1= C1Vin[n]Q1= -C1Vin[n]Q = -C2Vout[n-1]/2Q = C2Vout[n-1]/2Differential Switch-Cap CircuitVout+[n]Vout-[n]Vin+[n]Vin-[n]C2C1C2Vout[n] = Vout[n-1] + -2(C1/C2) (Vin[n])• We connect the capacitor to the charge summing node(3), [n] cycle: φ2Q = -C2Vout[n-1]/2 + C1Vin[n]Q = C2Vout[n-1]/2 -C1Vin[n]Differential Switch-Cap CircuitVout+[n]Vout-[n]Vin+[n]Vin-[n]C2C1C2• We disconnect the capacitor from the charge summing node, and return to our initial case(4), [n] cycle(Output unchanged)Vout[n] = Vout[n-1] – 2 (C1/C2) Vin[n]~0Stray Insensitive Circuits• Discussed issue of stray insensitive circuits• Discussed two typically used circuits, one single ended and one differential