1. First assume the process and its page table fit and stay in memory while the program executes, and there is no TLB or cache. What is the ema for this system?2. Now assume there is a TLB. What is the ema for this system? Include l, the time for the TLB lookup in your equation.3. Now consider a virtual memory system with a TLB where the process can grow larger than the memory, and the page may not be in memory (note that page fault can occur now). What is the ema now? Assume that the page table is always in memory.4. Now what is the ema for the same system except that the page table entry itself may not be in memory?5. Now assume that there is a first level cache for data accesses. Let ca be the time to access the cache. Assume that the TLB access must be completed first before the cache can be accessed. This, because the physical address is used to index and tag the cache. What is the ema now?C. (20) Replacement policy. Assume that you have 3 frames and you get the following sequence of page requests: A,B,C,D,E,D,A,A,B,C,C,B,A,E,D,A1. Show the replacement for FIFO and LRU, and calculate the number of page faults.1. Specify and justify the number of segments.2. Calculate the total size of ALL page tables (i.e., the sum of page table sizes including all segments). Assume inverted page table is used for all segments, and 128Kbyte SRAM is available as total physical memory. Assume that frames are assigned in proportion to segment size. Show the content of a page table entry (PTE).3. Specify hardware support to make address translation fast. Explain how it works.4. Draw a picture including ALL components of your system. In your figure show the page table for one segment only (similar as we have shown for the MULTICS scheme in lecture notes). It should be clear how a logical address is translated into a physical one.5. Draw a picture assuming there is a first level cache.E. (20pts) Synchronization and Deadlocks. The dining-philosophers problem.ECE397A Operating Systems – FINAL EXAM, 2002Instructions: - Put your name and student number on the exam books! - The exam is closed book and closed notes. - You have 1.5 hours to complete the exam. - First read the entire exam and then budget your time accordingly. Don't waste your time giving details that the question does not request. - Max score is 100. - Good luck!A. (20 pts) Short Answers (be short!)1. List the content of PCB.2. What is the advantage of using threads compared to processes?3. What is the difference between binary and counting semaphores?4. List three of the four necessary conditions for deadlock to occur.5. What is the difference between deadlock prevention and deadlock avoidance? 6. What happens during swapping and when it is used? 7. What happens during a page fault? 8. What happens during trashing (in the memory system) and why it happens?9. What is Belady’s anomaly? 10. What is a symbolic link in a file system and what is the problem with supporting links?B. (20 pts) Performance of Paged Systems. This question asks you to compute the effective memory access time (ema) in symbolic terms for different hardware implementations of paging. Let ma be the time to read or write a value in memory. Define other terms (e.g., TLB hit rate, page faults, cache hit rate) as youneed them. In all questions ignore the instruction memory related cache, TLB, and paging aspects. Before showing theequations show a table containing all your notations (e.g., in left column have variables, in right column what it means) and other assumptions you may have.1. First assume the process and its page table fit and stay in memory while the program executes, and there is no TLB or cache. What is the ema for this system?2. Now assume there is a TLB. What is the ema for this system? Include l, the time for the TLB lookup in your equation.3. Now consider a virtual memory system with a TLB where the process can grow larger than the memory, and the page may not be in memory (note that page fault can occur now). What is the ema now? Assume that the page table is always in memory. 4. Now what is the ema for the same system except that the page table entry itself may not be in memory?5. Now assume that there is a first level cache for data accesses. Let ca be the time to access the cache. Assume that the TLB access must be completed first before the cache can be accessed. This, because the physical address is used to index and tag the cache. What is the ema now?1C. (20) Replacement policy. Assume that you have 3 frames and you get the following sequence of page requests: A,B,C,D,E,D,A,A,B,C,C,B,A,E,D,A1. Show the replacement for FIFO and LRU, and calculate the number of page faults.2. D. (20pts) Segmentation with Paging. Design a virtual memory management scheme that uses segmentation with paging. Use 32 bit addresses and 1Kbyte page sizes.1. Specify and justify the number of segments.2. Calculate the total size of ALL page tables (i.e., the sum of page table sizes including all segments). Assume inverted page table is used for all segments, and 128Kbyte SRAM is available as total physical memory. Assume that frames are assigned in proportion to segment size. Show the content of a page table entry (PTE).3. Specify hardware support to make address translation fast. Explain how it works. 4. Draw a picture including ALL components of your system. In your figure show the page table for one segment only (similar as we have shown for the MULTICS scheme in lecture notes). It should be clear how a logical address is translated into a physical one.5. Draw a picture assuming there is a first level cache.E. (20pts) Synchronization and Deadlocks. The dining-philosophers problem. Access to food is the critical section, each Philosopher needs 2 chopsticks to eat.The philosophers are either eating or thinking.1. Check the solution below and identify how deadlock can occur. Use a Resource –allocation graph. Show your work.1. Modify the code to avoid deadlock.// Shared data semaphore chopstick[5]; // Initially all values are 1// Pseudo code for Philosopher i:do {wait(chopstick[i]) // grab left chopstickwait(chopstick[(i+1) % 5]) // right one …eat …signal(chopstick[i]); // put left on tablesignal(chopstick[(i+1) % 5]); // put back right …think …} while