Signature-Based Testing for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links Mohamed Abbas1, Kwang-Ting (Tim) Cheng1,2, Yasuo Furukawa3, Satoshi Komatsu1 and Kunihiro Asada1 {mohamed, komatsu}@VDEC.u-tokyo.ac.jp, [email protected], [email protected], [email protected] 1VLSI Design & Education Center, The University of Tokyo, Tokyo 113-0032, Japan 2 Department of Electrical and Computer Engineering, University of California, Santa Barbara 3ADVANTEST Corporation, Gunma 370-0718, Japan Abstract: This paper presents a cost-effective test methodology for adaptive equalizers which follow the digitally-assisted analog design style. By observing the states in the digital adaptation engine during or after the adaptation process in response to the test stimulus, the health of the adaptive equalizer can be determined. We propose two different types of signatures, namely static and dynamic signatures, based on the states of the digital adaptation engine for fault detection. The static signatures are derived from states after the adaption process converges and the dynamic ones from the state sequences sampled during adaption. Such signatures, combined with a variety of test stimuli, enable the detection of many hard-to-detect faults which cannot be detected by existing approaches. Our experimental results demonstrate the effectiveness and efficiency of the proposed method. 1. Introduction Advances in integrated circuit (IC) fabrication technology have enabled the design of many high-performance digital systems. These systems require efficient communication between multiple chips to achieve required system performance. The PHY bit rate has increased by one order of magnitude in the past eight years [1]. The drive to higher bandwidth interface has resulted in the adoption of high-speed serial links (HSSL). The large-scale integration creates significant challenges not only in designing these high-performance interface circuits but also in testing them in a noisy SoC environment. Although HSSL used in digital interfaces is similar to that used in analog communication channel, the procedure used for testing analog interfaces is not directly applicable for testing digital interfaces for many reasons. Among these are higher signal counts, higher production volume and lower average selling price. For a HSSL, the data transmitted is originally a digital signal. However, low signaling voltages, high speed and a limited channel bandwidth make the signal at the receiver (Rx) input no longer digital as illustrated in Figure 1. Therefore, equalization at the receiver is required to mitigate the problem [2]. To assure the equalizer quality, an efficient testing methodology is needed. One of the straight forward ways is driving the equalizer output signal off-chip and using a high bandwidth oscilloscope to measure the eye quality. However, the filtering nature of the routing and bonding wires would degrade the high frequency components and hence the signal appears on the scope will not match the actual signal on-chip. Furthermore, this method is time-consuming and too costly for production test. Several DFT-based methods have been proposed in the past few years. Several versions of on-die waveform capturing and eye-opening monitor techniques are presented in [3][4][5][6]. The on-chip solution provides the self-test capability; however, the hardware overhead is high and may be unacceptable for some commercial applications. External loopback testing [7][8] is another alternative; however, the known fault-masking issues of loopback testing make it far from an optimal solution. In [9][10], the authors proposed a methodology for testing and characterizing digitally-assisted adaptive equalizers. Specific test stimuli are applied for adaptation. After the adaptation process converges, the digital values of the tap coefficients in the equalizer are observed for fault detection. This method demonstrates that the digital adaptation unit, which is commonly available in modern adaptive equalizers, offers significantly better controllability and observability for accessing the analog signals for the testing purpose. However, due to the limited types of test stimuli applied and only very limited information extracted from the observed tap coefficients, a fraction of the hard-to-detect faults cannot be covered, especially for complex decision-feedback equalizers. In this paper, we present an improved and more general methodology for testing the adaptive systems that follow the digitally-assisted analog design style. Similar to the approach suggested in [9][10], fault detection is based on the observation of tap coefficients in the digital adaptation unit. We propose to extract both static and dynamic signatures from the waveforms of the tap coefficients. For the new dynamic-signature-basedtechnique, fault detection is made based on sampling and integrating the states of the digital adaptation engine during the convergence process. For the static-signature-based technique, fault detection is made by providing suitable test stimuli and observing the states after convergence. To gain the required observability and controllability, only very minor modification in the digital adaptation engine, which enables both on-line and off-line scan of the tap-coefficient registers. We also identify a variety of test stimuli which can be combined with static- and dynamic-signature based observation to achieve better detection of hard-to-detect faults. The rest of the paper is organized as follows. The digitally-assisted analog design style and its impact on testability is briefly summarized in Section 2. The background of adaptive equalizers and the adaptation algorithms is reviewed in Section 3. Our test methodology as well as application examples are presented in Section 4. The experimental results and discussion are given in Section 5 followed by the conclusion in Section 6. 2. Digitally-Assisted Analog Design The area and power consumption of analog functions scale at a much slower rate than those of digital circuitry. At the same time, as the technology continues to scale, the lower supply and relatively higher process variations makes it more difficult to design high performance and/or high resolution analog circuits. The adoption of digitally-assisted analog design style comes as a breakthrough to address this challenge [11]. For such designs, on-chip digital control and