Eric Jackowski734 Proposal FFT SurveyThe FFT is an algorithm used by many DSP applications, so I plan to do a survey paper on the FFT algorithm involving the concepts from class. I will focus the survey on the use of systolic arrays, pipelining, retiming and unfolding of the FFT algorithm. I will also look into efficient memory organizations and algorithm transformations for the FFT algorithm. Along with the above, I would like to present how each technique can possibly lead to higher performance and lower power. In completion of this survey, I would like to address some future research that can be done and have a complete understanding of the best fft for a certain application.Below are papers I have found that contain the main ideas of the survey. IEEEMinimizing the memory requirement for continuous flow FFT implementation: continuous flow mixed mode FFT (CFMM-FFT)Design of an efficient variable-length FFT processorDesign and implementation of a parallel real-time FFT processorTwiddle-factor-based FFT algorithm with reduced memory accessPerformance analysis of a 64-point FFT/IFFT block designed for OFDM technique used in WLANsEasily testable and fault-tolerant FFT butterfly networksA radix-2 FFT algorithm for modern single instruction multiple data (SIMD) architecturesA delay spread based low power reconfigurable FFT processor architecture for wireless receiverA low-power and domain-specific reconfigurable FFT fabric for system-on-chip applicationsA genetic algorithm for the optimisation of a reconfigurable pipelined FFT processorNew in-place strategy for a mixed-radix FFT processorA 2048 complex point FFT processor using a novel data scaling approachA new memory reference reduction method for FFT implementation on DSPFast Fourier Transform for high speed OFDM wireless multimedia systemA novel low-power reconfigurable FFT processorConflict-free parallel memory access scheme for FFT processorsA coefficient memory addressing scheme for VLSI implementation of FFT processorsA dynamic scaling FFT processor for DVB-T applicationsNovel low power pipelined FFT based on subexpression sharing for wireless LAN applicationsA new method for accelerating the FFT algorithm in massive image processingParallel implementation of 1-D fast Fourier transform without inter-processor communicationsA small-area high performance 512-point 2-dimensional FFT single-chip processorA triple port RAM based low power commutator architecture for a pipelined FFT processorImplementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 /spl mu/m bulk CMOSGeneral FFT pruning algorithmA 2048 complex point FFT architecture for digital audio broadcasting systemA hardware efficient control of memory addressing for high-performance FFT processorsSome New Parallel Fast Fourier Transform AlgorithmsACMHigh-level low power design II: A VLSI array processing oriented fast fourier transform algorithm and hardware implementationSynthesis of pipelined DSP accelerators with dynamic schedulingOptimizing computations for effective block-processingComputing the discrete Fourier transform on FPGA based systolic arrays Chris Dick Compilation for a high-performance systolic arrayHigh-level low power design II: A VLSI array processing oriented fast fourier transform algorithm and hardware implementationFPGA circuits and architectures: Design of a high performance FFT processor based on
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