Very Short Answer:(1) (2) What are the 4 different types of control flowchanges?(2) (1) Is it possible to design a flawless architecture?(3) (1) Peak performance does or does not track observed performance.(4) (1) If I am more interested in code size than performance, I will choose which kind ofinstruction encoding?(5) (1) Ignoring instruction set issues, What makes pipelining hard to implement?(6) (1) Is MIPS an accurate measure for comparing performance among computers?(7) (1) Out of Order completion makes supporting what very difficult?(8) (1) Are wire delays or transistors more likely to be the most significant limit on clock fre-quencyinthe future?Short Answers:(9) (2) Most silicon dies are fairly small. Whyare theynot bigger?(10) (2) Describe what the geometric mean is, and what the biggest drawback to using it is.(11) (3) Write down the 3-term CPU performance equation developed in class.-1-(12) (8) List the 5 classes of benchmarks, give anexample for each class, and tell me what theperfect benchmark would be.(13) (6) There are 3 kinds of Hazards. List and give brief descriptions of all three.(14) (6) There are 3 kinds of dependencies. List and give brief descriptions of all three.-2-(15) (10) Compare and contrast Tomasulo’salgorithm with Scoreboarding. (Convince meyou understand both - in other words, explain what theyare, howtheywork, whytheywork, howtheydiffer,how theyare the same, etc.)-3-(16) (10) Compare and contrast Superscalar with VLIW.Describe each, and list the advan-tages and disadvantages of each approach.-4-(17) (10) Determine the total branch penalty for a branch target buffer assuming there is a 2cycle penalty if the branch is not in the buffer and the branch is actually taken, and also a2cycle penalty if the branch is in the buffer but incorrectly predicted to be taken. Makethe following assumptions about the prediction accuracyand hit rate:60% of all branches are taken.Forinstructions in the buffer,the prediction accuracyis90%Forbranches predicted taken, the hit rate in the buffer is 90%-5-(18) (10) Asimple hardware implementation of the basic 5-stage RISC pipeline uses the EXstage hardware to calculate the branch instruction comparison, and does not deliverthetarget PC to the Instruction Fetch unit until the clock cycle in which the branch instruc-tion reaches the MEM stage. Control hazard stalls can be reduced by adding hardware toresolvethe branch condition in the ID stage, but doing so might reduce performance incertain circumstances. Howdoes determining the branch outcome in the ID stage havethe potential to increase data hazard stall cycles?-6-(19) (24) Consider the following three processors:A) A simple 2-issue machine (Curly) running with a clock rate of 1 GHZ and achieving apipeline CPI of 1.0. This processor has a cache system that yields 0.01 misses per instruc-tion.B) A deeply pipelined version of the same machine (Larry) with slightly smaller cachesand a 1.2 GHZ clock rate. The pipeline CPI of the processor is 1.2, and the smaller cachesyield (on average) 0.015 misses per instruction.C) A speculative superscalar machine with a 64-entry instruction window(Moe). Itachieves50% of the ideal issue rate of 9 instructions/cycle. This processor has the smallestcaches, which leads to 0.02 misses per instruction, but is able to hide 10% of the misspenalty on every miss because it does dynamic scheduling. This processor has an 800 MHZclock.Assume that the main memory time (which sets the miss penalty) is 100 ns. Determine the rela-tive performance of these three