CS M152B Spring 2003 Project 1 4 bit ALU Design You are asked to build a 4 bit asynchronous ALU that can do addition subtraction logical AND logical OR increment and decrement The top level schematic is shown in the following figure Cout zero A 3 0 S 3 0 B 3 0 ALU ctrl Cin The following is the functional truth table ALU Ctrl 000 001 010 011 100 101 Function S A B S A B S A B bitwise AND S A B bitwise OR S A 1 S A 1 the output zero is 1 when S is 0000 otherwise zero is 0 DON T DO Behavioral VHDL The main design goal is to minimize the size of your design You are welcome to use Schematic Structural VHDL CORE IP or any combination of the above More on the back Simulation With ModelSim For A 910 10012 B 310 00112 Show TA the results of the simulation of each function The results should be ALU Ctrl 000 001 010 011 100 101 Function S A B S A B S A B bitwise AND S A B bitwise OR S A 1 S A 1 Result S 1210 11002 S 610 01102 S 110 00012 S 1110 10112 S 1010 10102 S 810 10002 Simulate each function with some other numbers for A and B of your choice just to make sure that it really works The End of the Project 1 Report should include Design approach Design block diagram Size of the design the SLICEs number Simulation results including waveforms Extra credit work if any