1CS365 1Single Cycle Data PathCS 365 Lecture 6Prof. Yih HuangCS365 2 We're ready to look at an implementation of the MIPS Simplified to support only:– memory-reference instructions: lw, sw– arithmetic-logical instructions: add, sub, and, or, slt, nor– control flow instructions: beq, jMIPS Lite2CS365 3 Generic Implementation:– use the program counter (PC) to supply instruction address– get the instruction from memory– read registers– use the instruction to decide exactly what to do All instructions use the ALU after reading the registers. Why? – memory-reference? arithmetic? control flow?CS365 4State Elements Clocks used in synchronous logic – when should an element that contains state be updated?Clock TimeClockPulseFalling EdgeRaising Edge3CS365 5 Change of state (value) is based on the clock Latch: whenever the inputs change, and the clock is asserted Flip-flop: state changes only on a clock edge(edge-triggered methodology)Latches and Flip-flopsCS365 6D-latchQCD_QDCQ4CS365 7D flip-flop QQ_QQ_QD latchDCD latchDDCCDCQCS365 8Register Similar to the D Flip Flop:– N-bit input and output– Write Enable input Write Enable:– negated (0): Data Out will not change– asserted (1): Data Out will become Data InClockData InWrite EnableN NData Out Notice that clock input is inversed.– Value changes occur on raising edges5CS365 9 Built using D flip-flops Two read ports One write port Write effects seen in the next cycleRegister FileRegisterFileRegisterFile5Read Reg # 15Read Reg # 25RegWrite32Write Data32ReadData 132ReadData 2Write Reg # CS365 10Implementing Two Read PortsM u xRegister 0Register 1Register n – 1Register nM u xRead data 1Read data 2Read register number 1Read register number 26CS365 11Writing Register File The clock determines when to writen-to-1 decoderRegister 0Register 1Register n – 1CCDDRegister nCCDDRegister numberWriteRegister data01n – 1nCS365 12PCInstructionmemoryReadaddressInstruction[31–0]Instruction [20 16]Instruction [25 21]AddInstruction [5 0]MemtoRegALUOpMemWriteRegWriteMemReadBranchRegDstALUSrcInstruction [31 26]416 32Instruction [15 0]00Mux01ControlAddALUresultMux01RegistersWriteregisterWritedataReaddata 1Readdata 2Readregister 1Readregister 2SignextendMux1ALUresultZeroPCSrcDatamemoryWritedataReaddataMux1Instruction [15 11]ALUcontrolShiftleft 2ALUAddressSingleCycle Datapath7CS365 13Control Signals ALU Operation (ALUOp3:ALUOp0)0000 and0001 or0010 add0110 sub0111 set-on-less-than1100 norCS365 14 ALUsrc: determine the 2ndoperand to ALU– 0: from the 2ndregister read port– 1: sign-extended immediate PCsrc: determines the input to PC– 0: PC+4– 1: PC+Offset MemRead/MemWrite: enable/disable memory read/write8CS365 15 RegWrite: determined whether a write is performed on the register file. MemToReg: determine the input to register write port– 1: memory read port– 0: ALU output RegDst: determine the register # to be written– 0: rt– 1: rdCS365 16Instruction Executions ADD: rd = rs + rt LW: $rt = Memory[$rs + Offset]OpSRCALURegWritePCsrcMemReadMemWriteMem2RegRegDstOpSRCALURegWritePCsrcMemReadMemWriteMem2RegRegDst9CS365 17Instruction Executions BEQ: PC = PC+Offset, if rs==rtOpSRCALURegWritePCsrcMemReadMemWriteMem2RegRegDstOpSRCALURegWritePCsrcMemReadMemWriteMem2RegRegDst SW: Memory[$rs + Offset] = $rtCS365 18Generating Control Signals ALUOp0 =  ALUOp1 = ALUOp2 = ALUOp3 =10CS365 19 ALUsrc =  PCsrc =  MemRead = MemWrite =  RegWrite =  Mem2Reg =CS365 20Discussions Can the datapath support– addi ?– j ?– jr ?11CS365 21Clock Cycle Times A clock cycle must accommodate the slowest operation in the data path Consider load word– Fetch instruction– Read register file– ALU– Read memory– Write register file Clock cycle ≥ 2×RegDelay + ALU-Delay + 2×MemDelayCS365 22Problems Delays are NOT born equal.– Memory delays far longer than others Things get even worse when complicated operations (e.g., floating point arithmetic) are introduced. Conclusion: one should not expect each instruction to use exactly one cycle time.12CS365 23Solution Allow some instructions to take longer to complete than others. A multi-cycle data path needed More sophisticated control strategy