Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Slide 39Slide 40Slide 41Slide 42Slide 43Slide 44Slide 45What You Need to Knowfor Project ThreeDave EckhardtSteve MuckleCarnegie Mellon University 1OverviewIntroduction to the Kernel ProjectMundane Details in x86registers, paging, the life of a memory access, context switching, system calls, kernel stacksLoading ExecutablesStyle Recommendations (or pleas)Attack StrategyA Quick Debug StoryCarnegie Mellon University 1Introduction to the Kernel ProjectP3:P2 :: P2:P1!P2•Stack, registers, stack, race conditions, stackP3•Stack, registers, page tables, scheduling, races...You will become one with program executionP1: living without common assumptionsP3: providing assumptions to usersCarnegie Mellon University 1The P3 Experience•Goals/challenges•More understanding•Of OS•Practice with synthesizing design requirements•More code•More planning•More organization•More quality!•RobustCarnegie Mellon University 1Introduction to the Kernel Project: Kernel FeaturesYour kernels will feature:- preemptive multitasking- multiple virtual address spaces- a “small” selection of useful system calls- robustness (hopefully)Carnegie Mellon University 1Introduction to the Kernel Project: Preemptive Multitasking Preemptive multitasking is forcing multiple user processes to share the CPUYou will use the timer interrupt to do thisReuse your timer code from P1 if possibleCarnegie Mellon University 1Introduction to the Kernel Project: Preemptive MultitaskingSimple round robin scheduling will suffice•Some system calls will modify the sequence•Think about them before committing to a designContext switching is tricky but coolAs in P2, creating a new process/thread is hard•Especially given memory sharingAs in P2, exit is tricky too•At least one “How can I do that???” questionCarnegie Mellon University 1Introduction to the Kernel Project: Multiple Virtual Address SpacesThe x86 architecture supports pagingYou will use this to provide a virtual address space for each user processEach user process will be isolated from othersPaging will also protect the kernel from usersCarnegie Mellon University 1Introduction to the Kernel Project: System CallsYou used them in P2Now you get to implement themExamples include fork, exec, and thread_forkThere are easier ones like getpidThe core cluster – must work solidly•fork(), exec()•exit(), wait()Carnegie Mellon University 1Mundane Details in x86We looked at some of these for P1Now it is time to get the rest of the storyHow do we control processor features?What does an x86 page table look like?What route does a memory access take?How do you switch from one process to another?Carnegie Mellon University 1Mundane Details in x86: RegistersGeneral purpose regs (not interesting)Segment registers (somewhat interesting)- %cs, %ss, %ds, %es, %fs, %gs%eip (a little interesting)EFLAGS (interesting)Control Registers (very interesting)- %cr0, %cr1, %cr2, %cr3, %cr4- esp0 field in hardware taskCarnegie Mellon University 1Mundane Details in x86: General Purpose RegistersThe most boring kind of register%eax, %ebx, %ecx, %edx, %edi, %esi, %ebp, %esp%eax, %ebp, and %esp are exceptions, they are slightly interesting- %eax is used for return values- %esp is the stack pointer- %ebp is the base pointerCarnegie Mellon University 1Mundane Details in x86: Segment Selector RegistersSlightly more interesting%cs specifies the segment used to access code (also specifies privilege level)%ss specifies the segment used for stack related operations (pushl, popl, etc)%ds, %es, %fs, %gs specify segments used to access regular dataMind these during context switches!!!Carnegie Mellon University 1Mundane Details in x86:The Instruction Pointer (%eip)It’s interestingCannot be read from or written to directly•(branch, call, return)Controls which instructions get executed‘nuff said.Carnegie Mellon University 1Mundane Details in x86: The EFLAGS RegisterIt’s interestingFlag city, including interrupt-enable, arithmetic flags•“Alignment check” offCarnegie Mellon University 1Mundane Details in x86: Control RegistersVery interesting!An assortment of important flags and values%cr0 contains powerful system flags that control things like paging, protected mode%cr1 is reserved (now that’s really interesting)%cr2 contains the address that caused the last page faultCarnegie Mellon University 1Mundane Details in x86: Control Registers, cont.%cr3 contains the address of the current page directory, as well as a couple paging related flags%cr4 contains… more flags (not as interesting though)- protected mode virtual interrupts?- virtual-8086 mode extensions?- No thanksCarnegie Mellon University 1Mundane Details in x86: RegistersHow do you write to a special register?Most of them: movl instructionSome (like CRs) you need PL0 to accessWe will provide inline assembly wrappersEFLAGS is a little different, but you will not be writing directly to it anywayCarnegie Mellon University 1Mundane Details in x86: The Life of a Memory AccessLogical AddressLinear AddressPhysical AddressSegmentationPaging(consists of 16 bit segment selector, 32 bit offset)(32 bit offset)(32 bit offset)Carnegie Mellon University 1Mundane Details in x86: The Life of a Memory AccessLogical AddressLinear AddressSegmentation(consists of 16 bit segment selector, 32 bit offset)(32 bit offset)The 16 bit segment selector comes from a segment register (%CS, %SS implied)The 32 bit offset is added to the base address of the segmentThat gives us a 32 bit offset into the virtual address spaceCarnegie Mellon University 1Mundane Details in x86:SegmentationSegments need not be backed by physical memory and can overlapSegments defined for these projects:Kernel Code Kernel Data User Code User Data0xFFFFFFFF0x00000000Carnegie Mellon University 1Mundane Details in x86: SegmentationFor Project 3 we are abusing segmentation•All segments “look the same”•Confusing, but simplifies life for you•See 15-410 segmentation guide on web siteCarnegie Mellon University 1Mundane Details in x86: The Life of a Memory AccessLinear AddressPhysical AddressPaging(32 bit offset)(32 bit offset)Top 10 bits index into page directory, point us to a page tableThe
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