University of Southern California Viterbi School of Engineering EE577A VLSI System Design Interconnect Modeling References syllabus textbook Professor Massoud Pedram s slides online resources Shahin Nazarian All rights reserved Background Shahin Nazarian All rights reserved 2 Types of Interconnect and Performance Metrics Dimension based classification Local Intermediate semi global Global Function based classification Signaling Clocking Power ground distribution Signaling Propagation delay Power dissipation Data reliability Noise Area Power Lines Supply reliability Shahin Nazarian All rights reserved Reliability Electromigration Clocking Timing uncertainty skew and jitter Power dissipation Slew rate 3 RLCG Model of Interconnection RLCG parasitic consists of resistance inductance capacitance and conductance An RLGC interconnection tree with typical signal waveforms at nodes A and B showing signal delay and various delay components Shahin Nazarian All rights reserved 4 When to Use Transmission Line Equations If time of flight determined by light speed across interconnection line is much shorter than rise fall time then wire can be modeled as a capacitive load or as lumped or as distributed RC network otherwise it must be modeled as transmission lines with inductance Simple rule of thumb l rise fall 2 5 transmission line modeling either transmission line l l 2 5 rise fall 5 or lumped modeling l rise fall 5 lumped modeling l is the interconnect line length and is the propagtion speed Optional http en wikipedia org wiki Velocity of propagation Shahin Nazarian All rights reserved 5 Interconnect Capacitances h tild Interconnect running above substrate Inter layer dielectric ILD material is known Influence of fringing electric fields upon the parasitic wire capacitance Shahin Nazarian All rights reserved 6 Parallel Plate Capacitance Equation Current W L H Dielectric tild Electric Fields Substrate C pp Shahin Nazarian All rights reserved ild tild WL 7 Wire Capacitance W H Fringing Fields Lines H Conductor Cwire C pp C fringe W H 2 tild H W ild 2 ild 2 L tild tild log H L denotes the interconnect length Shahin Nazarian All rights reserved 8 Capacitive Coupling Components Transition in one line can cause noise in another line Signal crosstalk Co Co far victim aggressor ICm near Rs Rs Shahin Nazarian All rights reserved 9 Interconnect Resistance Estimation h tild Rwire l l Rsheet wh w where Rsheet h characteristic resistivity of the interconnect material Rsheet sheet resistivity of the line square Shahin Nazarian All rights reserved 10 Resistivity and Sheet Resistivity Resistance Shahin Nazarian All rights reserved 11 Interconnect Scaling Scenario Chip area increases with each node Device dimensions are scaled as discussed before Typical scaled wires are Longer chip area scaling Narrower and closer to one another minimum dimension scaling Fatter taller or look taller to reduce sheet resistivity Shahin Nazarian All rights reserved 12 Scaling for Capacitances and Resistance of a Global Line Assume that with technology scaling L of a global VLSI interconnect line increases its H remains the same while its W tILD and D decrease see drawing CIMD t ILD Shahin Nazarian All rights reserved CILD D 13 Scaling for Capacitances and Resistance of a Global Line Cont Both the inter layer capacitance CILD and intermetal capacitance CIMD increase although CIMD increases at a faster rate As a result Cwire increases The wire resistance Rwire increases even more rapidly Notice that the line aspect ratio defined as H W increases Also note the one sided fringing field calculation due to the presence of a parallel adjacent wire H C IMD t ILD CILD D Shahin Nazarian All rights reserved W L ILD ILD L HL IMD 2 CILD CIMD t ILD D t log ILD H L Cwire CILD CIMD Rwire Assume IMD ILD WH H W H L2 2 wire 0 69 ILD t t D WH ILD ILD log H 14 Typical VLSI Interconnect Dimensions 0 18um technology node Local Intermediate Global width um 0 28 0 35 0 80 space um 0 28 0 35 0 80 thickness um 0 45 0 65 1 25 tILD um 0 65 0 65 0 65 kILD 3 5 3 5 3 5 space um 0 15 0 20 0 50 thickness um 0 30 0 45 1 20 tILD um 0 30 0 30 0 30 kILD 2 8 2 8 2 8 space um 0 10 0 14 0 45 thickness um 0 20 0 35 1 20 tILD um 0 20 0 20 0 20 kILD 2 2 2 2 2 2 90nm technology node Local Intermediate Global width um 0 15 0 20 0 50 65nm technology node Local Intermediate Global width um 0 10 0 14 0 45 Shahin Nazarian All rights reserved 15 Calculation of Interconnect Delay Lumped RC Delay Model a R b C Simple lumped model C 2 C 2 section model a Simple lumped RC R c R 2 R 2 C T section model model of an interconnect line Assume that the capacitance is initially discharged Input is a rising step input pulse at time t 0 Vout t VDD V 50 VDD t 1 e RC pLH 1 e RC 63 2 V RC DD pLH 0 69RC b c The p and T model of the same line which improve accuracy Shahin Nazarian All rights reserved 16 The Elmore Delay Cont The Elmore delay is an approximation of actual delay Let Ti denote the subtree rooted at node i for i 1 2 N Let Pi denote the unique path from input node to node i Let Pij Pi Pj denote the portion of the path which is common between paths Pi and Pj Assuming input is a step pulse at t 0 the Elmore delay at node i is calculated as follows Resistance oriented Formula E i Rj for all j Pi Capacitance oriented Formula N Di C j j 1 Shahin Nazarian All rights reserved Ck for all k Ti for all k Pij Rk 17 Elmore Delay Calculation Example 0 Resistance oriented Formula D 4 R1 C1 C2 C3 C4 C5 R2 C 2 C4 C5 R4 C4 Capacitance oriented Formula D 4 C1 R1 C 2 R1 R2 C 3 R1 C 4 R1 R 2 R 4 C 5 R1 R 2 Shahin Nazarian All rights reserved 18 Distributed RC Ladder Network C The transient response of an interconnect line can be more accurately represented using an RC ladder network Let l denote the total length of interconnect in the limit of N going to infinity r and c denote resistance and capacitance per unit length of interconnect out 63 2 VDD RC r c l 2 2 2 Shahin Nazarian All rights reserved for N 19 Comparison Between Lumped and Distributed RC Delay We estimate propagation delay using RC time constants assuming that the time taken for a signal to reach 63 2 of its final value approximates the switching point of an inverter Use 0 69RC to calculate 50 prop delays Shahin Nazarian All rights reserved 20 Elmore Delay as a Bound for RC Trees The Elmore delay measure is an upper bound on the actual 50 delay of an RC tree response Elmore delay is the true delay corresponding to an infinitely slow