University of Southern California Viterbi School of Engineering EE577A VLSI System Design Static Characteristics and Noise Margin References Syllabus textbooks Professor Massoud Pedram s slides online resources Shahin Nazarian All rights reserved Ideal Inverter Threshold Voltage VM For 0 Vin VM VDD 2 For VM Vin VDD 0 Vin VM VM Vin VDD input is interpreted as a logic 1 Shahin Nazarian All rights reserved Vout VDD logic 1 Vout 0 logic 0 input is interpreted as a logic 0 2 VTC There are two critical voltage points for which dVout dVin 1 VOH Max output voltage when output level is logic 1 VOL Min output voltage when output is level logic 0 VOH f VOL VOL VOL f VOH VOH VIL Maximum input voltage which can be interpreted as logic 0 VIH Minimum input voltage which can be interpreted as logic 1 Inverter threshold voltage VM defined as the point where Vin Vout transition voltage Shahin Nazarian All rights reserved VOL 3 Noise Margin NM Noise Margin for low signal levels NML VIL VOL Noise Margin for high signal levels NMH VOH VIH A narrow transition or uncertain region would allow larger noise margins therefore reducing the width of the uncertain region is desirable and an important design objective Illustration of noise margins Shahin Nazarian All rights reserved 4 Noise Immunity Shahin Nazarian All rights reserved 5 Resistive Load nMOS Inverter Shahin Nazarian All rights reserved 6 Calculation of VOH Vout VDD RL IR When Vin VT0 transistor is in cut off I R ID 0 VOH VDD Shahin Nazarian All rights reserved 7 Calculation of VOL Assume Vin VOH VDD Vin VT0 Vout Linear region IR VDD Vout RL Using KCL for output node IR ID VDD VOL RL kn 2 2 VDD VT0 VOL V2OL VOL can be numerically calculated from above Alternatively the above equation can be solved for VOL which results in VOL 1 1 2 2VDD VDD VT 0 VDD VT 0 kn RL kn RL kn RL Note Instead of memorizing the noise margin related equations one can use the definitions e g here for VOL and write a KCL based on the transistor mode e g here it is linear Shahin Nazarian All rights reserved 8 Calculation of VIL dVout dVin 1 at Vin VIL Vout Vin VT0 the transistor operates in saturation region KCL for the output node VDD Vout RL kn 2 Vin VT0 2 Differentiate both sides 1 RL dVout dVin kn Vin VT0 Substitute dVout dVin 1 1 1 RL 1 kn VIL VT0 VIL VT0 1 knRL 2 By substituting 2 into 1 Vout Vin VIL VDD knRL 2 VT0 1 knRL VT0 2 VDD 1 2knRL Shahin Nazarian All rights reserved 9 Calculation of VIH VIH is the larger of the two points at which slope is equal to 1 When Vin VIH Vout is slightly larger than VOL Vout Vin VT0 Linear mode therefore KCL for the output node VDD Vout RL kn 2 2 Vin VT0 Vout V2out 3 Differentiate both sides wrt Vin 1 RL dVout dVin kn 2 2 Vin VT0 dVout dVin 2Vout 2Vout dVout dVin By substituting dVout dVin 1 at Vin VIH 1 RL 1 kn VIH VT0 1 2Vout VIH VT0 2Vout 1 knRL 4 By substituting 4 into 3 VDD Vout RL kn 2 2 VT0 2Vout 1 knRL VT0 Vout Vout2 Positive solution Vout Vin VIH 2 3 VDD knRL 1 2 Substitute 5 into 4 Shahin Nazarian All rights reserved VIH VT 0 5 8 VDD 1 3 kn RL kn RL 10 Calculation of VIH Cont knRL plays an important role in determining the shape of the VTC VOH is determined primarily by VDD Adjustment of VOL receives primary attention VIL VIH are usually treated as secondary design variables For larger knRL values VOL becomes smaller and shape of the VTC approaches that of the ideal inverter Shahin Nazarian All rights reserved VTC of the resistive load inverter for different values of knRL 11 Power Consumption and Gate Area DC power consumption of the resistive load inverter circuit is found by considering two cases 1 Vin VOL low PDC 0 transistor is in cut off ID IR 0 2 Vin VOH high transistor is in linear region and Vout VOL ID IR VDD VOL RL Assuming Voltage is low 50 of time and high 50 of time PDC average VDD 2 VDD VOL RL The gate area depends on two parameters 1 W L ratio of the driver transistor approximated by the gate area W x L It can be 2 RL value Resistor area depends on fabrication technology Shahin Nazarian All rights reserved 12 Inverters with n Type MOSFET Load Resistive load inverter circuit is not suitable in most VLSI circuit designs because of large area occupied by the load resistor Use nMOS as the active resistor load Advantages smaller area and better performance Inverter with saturated enhancement type NMOS load Shahin Nazarian All rights reserved Inverter with linear enhancement type NMOS load 13 Depletion Load nMOS Inverter Advantages Sharp VTC transition and better noise margins Single power supply Smaller overall layout Downside fabrication process is more complicated DC power consumption Driver device enhancement type nMOS transistor with VT0 driver 0 Load depletion type transistor with VT0 load 0 nMOS a Inverter with depletion type VGS load 0 VGS load VT load VSB load Vout Shahin Nazarian All rights reserved nMOS load b Simplified equivalent circuit consisting of a nonlinear load resistor a non ideal switch controlled by input 14 Depletion Load nMOS Inverter Cont VSB load Vout threshold voltage is a function of Vout VT load VT 0 load 2 F Vout 2 F When Vout is low Vout VDD VT load depletion type load transistor is in saturation ID load kn load 2 VT load Vout 2 kn load 2 VT load Vout 2 When Vout is high Vout VDD VT load load transistor is in the linear region ID load kn load 2 2 VT load Vout VDD Vout VDD Vout 2 VTC can be constructed by setting ID driver ID load VGS driver Vin VDS driver Vout and solving Vout f Vin Shahin Nazarian All rights reserved 15 Depletion Load nMOS Inverter Cont Driver Load Operating Operating Region Region Vin Vout VOL VOH cut off linear VIL VOH saturation linear VIH small linear saturation VOH VOL linear saturation Shahin Nazarian All rights reserved Typical VTC of a depletion load inverter circuit 16 Calculation of VOH Vin VT0 driver transistor is in cut off load transistor is in linear region Vout VOH ID load 0 ID load kn load 2 2 VT load VOH VDD VOH VDD VOH 2 0 The only valid solution in the linear region is VOH VDD Shahin Nazarian All rights reserved 17 Calculation of VOL Vin VOH VDD driver transistor is in linear region and depletion type load is in saturation kdriver 2 2 VOH VT0 VOL VOL2 kload 2 VT load VOL 2 Temporarily neglect dependence of VT load on VOL resulting in VOL VOH VT 0 VOH VT 0 2 2 kload VT load VOL kdriver I The actual value of VOL is …