University of Southern California Viterbi School of Engineering EE577A VLSI System Design Transient Behavior of MOS Gates References syllabus textbook Professor Massoud Pedram s slides online resources Shahin Nazarian All rights reserved Background Stage Delay Gate Delay Interconnect Delay in out Near end node Far end node G1 Shahin Nazarian All rights reserved G2 B A D C 2 CMOS Inverter with a Single Lumped Load in out in Ceff out Ceff Cgd Cgs Cgb Oxide caps in Cdb Csb Junction caps out Ceff Shahin Nazarian All rights reserved 3 Miller Capacitance C V K V Q C V K V C K 1 C V Ceff K 1 Ceff 2C K 1 Ceff out C K K 1 Ceff out 2C Effective Capacitance increases because of Miller Effect Shahin Nazarian All rights reserved 4 Timing Related Definitions Propagation delays tdf pHL t1 t0 tdr pLH t3 t2 1 V50 VOL VOH 2 V10 VOL 0 1 VOH VOL V90 V90 VOL 0 9 VOH VOL V10 tA tB tfall tC tD trise Rise and Fall times aka transition times aka slews t fall t B t A trise t D tC Shahin Nazarian All rights reserved 5 Average Capacitance Current Method Let I avg HL average current during high to low output transition I avg LH average current during low to high output transition We can write 1 I avg HL ic Vin VOH Vout VOH ic Vin VOH Vout V50 2 1 I avg LH ic Vin VOL Vout V50 ic Vin VOL Vout VOL 2 Therefore pHL Cload VHL Cload VOH V50 I avg HL I avg HL pLH Cload VLH Cload V50 VOL I avg LH I avg LH Similar expressions may be written for rise fall time calculation Shahin Nazarian All rights reserved 6 Delay Calculation for Small Geometry MOS Current driving capability is significantly reduced by velocity saturation ID sat W vd sat Cox VDSAT VDSAT VDD VT Assume discharge and charge currents are approximated with the saturation current this shows the weak dependence of td in low geometry Better delay estimates possible with better current models such as Sakurai Newton current model t df Shahin Nazarian All rights reserved C load VDD 2 Wn d sat Cox VDD VT n 7 Delay Calculation for CMOS Gates Under Step Input Quick Approximate Formula Long channel devices quadratic current equations CloadVDD pHL kn VDD Vtn pLH 2 CloadVDD k p VDD Vtp 2 Short channel devices alpha power current equations With 1 3 1 6 pHL pLH Shahin Nazarian All rights reserved CloadVDD kn VDD Vtn CloadVDD k p VDD Vtp 8 Gate Delay for Ramp Input VDD ID p tr tf ic Vin Vin Vout Cload ID n tdf ramp tdf step tdr ramp tdr step Shahin Nazarian All rights reserved 2 2 t r 2 2 tf 2 2 9 Fast Ramp Inputs Let V1 Vin Vtn while V2 denote output voltage when input voltage reaches its final value Fast input transitions i e Tr in 2 pHL ramp or T f in 2 pLH ramp This corresponds to the case when the driver transistor is still saturated when the input voltage ramp reaches its final value here V2 V1 T f out 2 pHL step Tr out 2 pLH step Shahin Nazarian All rights reserved pHL ramp pHL step pLH ramp Tr in Vtn 1 2 6 VDD Vtp T f in 1 2 pLH step 6 VDD 10 Slow Ramp Inputs Slow input transitions i e Tr in 2 pHL ramp or T f in 2 pLH ramp Driver transistor leaves saturation while the input voltage is still ramping here V2 V1 For delay calculation there are two cases to consider V2 VDD 2 and V2 VDD 2 The exact expressions are intricate and involve the erf and ln functions respectively Output transition calculation requires a complicated derivation based on solving differential equations with appropriate initial values for different regions of transistor operation Shahin Nazarian All rights reserved 11 Approximate Gate Delay and Transition Time Calculation for Slow Ramp Inputs Tr in Vtn V DD Approximate expressions 2 for slow input transitions T f in Vtp pLH ramp pLH step ignoring the Miller 2 V DD capacitance which causes Vtn 1 over undershoots and also V DD T 2 f out pHL step causes short circuit V 1 pHL ramp tn current flow during the 2 Tr in V DD output transition V pHL ramp pHL step 1 Tr out 2 pLH step Notice that Tr in 2 pHL ramp pHL ramp pHL step 1 tp V DD Vtp 1 pLH ramp 2 T f in V DD Vtn VDD T f out 2 pHL step Shahin Nazarian All rights reserved 12 An Example Calculation for Ramp Input Consider an inverter driving load CL with tpHL step 100ps Calculate the gate delay and output fall time for a rising input with Tr in 25ps Assume Vtn VDD 1 4 Repeat calculation for Tr in 300ps Solution For fast ramp Tr in 25 ps pHL ramp pHL step Tr in Vtn 1 2 6 VDD 25 2 100 1 106 25 ps 6 4 T f out 2 pHL step 2 100 200 ps For slow ramp Tr in 300 ps pHL ramp Tr in Vtn 300 1 pHL step 100 137 5 ps 2 VDD 2 4 1 T f out 2 pHL step Vtn VDD 1 pHL ramp Vtn 2 Tr in VDD Shahin Nazarian All rights reserved 1 1 0 75 4 2 100 200 211 76 ps 1 137 5 1 0 708 2 300 4 13