University of Southern California Viterbi School of Engineering EE577A VLSI System Design Introduction References Professor Massoud Pedram s lecture slides books listed in the syllabus and online resources Shahin Nazarian All rights reserved EE577A Objectives Shahin Nazarian All rights reserved Two Terminal MOS Structure Under thermal equilibrium Mass Action Law np ni2 ni 1 45 1010 cm 3 If substrate is uniformly doped NA Typically 1014 to 1016 p p0 N A n p0 Shahin Nazarian All rights reserved ni2 NA 3 Structure of MOS Transistor The inverted surface layer is essential for current conduction The two n regions are added as the current conducting terminals Conventionally all terminal voltages are defined wrt VS Shahin Nazarian All rights reserved 4 Threshold Voltage Channel behavior is exactly as that of a metal gateoxide increase VG and surfaces is inverted as soon as surface potential reaches a critical threshold voltage VT0 Note that increasing VGS beyond VT0 will not increase the depletion region depth VDS would then allow current flow Shahin Nazarian All rights reserved 5 nMOS Accumulation Shahin Nazarian All rights reserved 6 nMOS Depletion Shahin Nazarian All rights reserved 7 nMOS Inversion Shahin Nazarian All rights reserved 8 nMOS Linear and Saturation Operations Operating in the linear region Operating at the edge of saturation Operating beyond saturation Shahin Nazarian All rights reserved 9 CMOS Processing Technology Steps Useful link http semiconductorglossary com LOCOS process Well and substrate contacts not shown M Pedram USC EE All rights reserved Shahin Nazarian 10 NMOS ID VDS and ID VGS Curves I D lin nCox W I D sat M Pedram USC EE All rights reserved Shahin Nazarian 2 2 V L GS nCox W 2 L 2 VT 0 VDS VDS VGS VT 0 2 11 Channel Length Modulation The channel is pinched off under saturation condition The pinch off point moves from the drain end towards source as VDS increases I Dsat 1 1 L 1 where L L L L L VDS L We can then write the saturation current as I D sat nCox W 2 L VGS VT 0 1 VDS M Pedram USC EE All rights reserved Shahin Nazarian 2 12 Substrate Bias Effect Applying a substrate voltage changes the threshold voltage VT VSB VT 0 2 F VSB 2 F We can simply replace the threshold voltage terms in linear mode and saturation mode current equations with VT VSB I D lin nCox W 2 V L GS 2 VT VSB VDS VDS 2 C W 2 I D sat n ox VGS VT VSB 1 VDS 2 L M Pedram USC EE All rights reserved Shahin Nazarian 13 Shahin Nazarian All rights reserved 14 MOSFET Current Voltage Equations a k a Shichman Hodges Equations nMOS transistor with kn kn W W nCox L L I D cutoff 0 VGS VT kn 2 2 VGS VT VSB VDS VDS 2 k 2 I D sat n VGS VT VSB 1 VDS 2 I D lin pMOS transistor with k p k p VGS VT VDS VGS VT VGS VT VDS VGS VT W W pCox L L I D cutoff 0 VGS VT 2 V 2 I D lin kp I D sat kp GS 2 2 VT VSB VDS VDS VGS VT VSB 1 VDS Shahin Nazarian All rights reserved 2 VGS VT VDS VGS VT VGS VT VDS VGS VT 15 Example For an n channel MOS transistor with n 600 cm2 V s Cox 7x10 8 F cm2 W 20 m L 2 m and VT0 1 0 V plot the relationship between ID and the terminal voltages k 600cm 2 V s 7 10 8 F cm 2 For Linear operation VGS VT 0 VGD VGS VDS VT 0 20 m 0 42 mA V 2 2 m VDS VGS VT 0 2 I D 0 21 mA V 2 2 VGS 1 VDS VDS Shahin Nazarian All rights reserved 16 NMOS Transistors in Series Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high A B X Y Y X if A and B A X B Y Y X if A OR B NMOS Transistors pass a strong 0 but a weak 1 Shahin Nazarian All rights reserved 17 PMOS Transistors in Series Parallel Connection PMOS switch closes when switch control input is low A B X Y Y X if A AND B A B A X B Y Y X if A OR B AB PMOS Transistors pass a strong 1 but a weak 0 Shahin Nazarian All rights reserved 18 Threshold Drops NMOS A device which is good in shorting its drain to the ground PMOS A device which is good in shorting its drain to VDD VDD PUN VDD S D VDD D 0 VDD VGS S CL VDD 0 PDN D VDD S CL 0 VDD VTn CL VGS VDD VTp S CL D NMOS passes a strong zero and a weak one PMOS passes a strong one and a weak zero Note NMOS gate 0 PMOS gate 1 are in high Impedance Shahin Nazarian All rights reserved 19 CMOS NOR2 Gate VDD A B F B Shahin Nazarian All rights reserved A B 0 0 0 1 1 0 1 1 F 1 0 0 0 A 20 Complex Static CMOS Gates In CMOS logic gates nMOS FETs are used to connect the output to GND whereas pMOS FETs are used to connect the output to VDD An nMOS FET functions as a pull down device when it is turned on gate voltage VDD A pMOS FET functions as a pull up device when it is turned on gate voltage GND VDD A1 A2 AN Pull up network A1 A2 AN Pull down network F A1 A2 AN input signals Shahin Nazarian All rights reserved pMOS FETs only nMOS FETs only 21 Shahin Nazarian All rights reserved 22 Reduction of Complex Gates to Inverters W W L L equivalent Z D VDD B 1 1 1 W W W L A L B L C VDD A C D OUT D A B C Z A D B C Note that reduction for worst case tpHL is W L worstcasedelay Z Shahin Nazarian All rights reserved 1 1 W MIN L D 1 1 1 1 W W W W L L L L C A B A 23 Sizing Complex CMOS Gates A B 8 6 C 8 6 4 3 D 4 6 OUT D A B C A D 2 1 B Shahin Nazarian All rights reserved 2C 2 24 Layout Design Stick Diagram Construction of the dual pull up graph from the pull down graph Shahin Nazarian All rights reserved 25 Stick Diagram Cont The number of diffusion breaks can be minimized by changing the ordering of the polysilicon columns A simple method for finding the optimum gate ordering is the Euler path approach Find a common Euler path for both pull down and pull up graphs The polysilicon columns can be arranged according to the sequence in Euler path Diffusion will be unbroken if identically labeled Euler …