EE 577A Homework 0 Spring 14 Nazarian Score Student ID First Name Last Name Assigned Saturday January 18 Due No submission is necessary Note Apply the following rule to any applicable problem that follows Write the parameter units right beside their numerical values in your formula and equations and verify that the final result has the right unit e g Having L 100nm and I 20 A for L I write 100nm 20 A 5nm A 1 50 Points Consider A CMOS Inverter with kp 50 A V2 and kn 100 A V2 W L n 10 W L p 20 VTN0 0 4V VTP0 0 5V VDD 2 5V Assume the equivalent output load capacitance Cload is 50fF a 10 Points Briefly explain what is body effect and channel length modulation b 10 Points Briefly explain what is progressive resizing c 10 Points Please list at least three undesirable effects of scaling of transistor size d 10 Points If you desire to design an inverter such that NMH NML then how do you size the NMOS and PMOS transistors of the inverter e 10 Points For a gate if we increase the widths of the transistors the corresponding propagation delays get decreased first but will get increased eventually if the widths continue increasing Please explain why it happens 2 5 Points Consider the following stick diagram Draw the transistor level schematic What boolean equation does the circuit implement 3 5 Points What is the problem in the MUX design shown below Hint power consumption 4 20 Points The boolean equation of the function is f a bc d a 10 Points Design a circuit that implements the function f with pass transistors ONLY Assuming all complementary inputs are available b 10 Points Draw the stick diagram of the CMOS compound gate that implements the function f 5 25 Points A 3 input minority gate outputs 0 if at least two of its inputs are true and outputs 1 otherwise a 10 Points Draw the transistor level of a CMOS compound gate to implement this minority gate Size the transistors such that the output resistance is the same as an inverter with Wp 3Wn EE577A Homework 0 Spring 2014 Shahin Nazarian b 10 Points Draw the stick diagram of this compound gate c 5 Points Draw the gate level of schematic using CMOS NAND NOR gates and inverters Compare the number of transistors used with a 6 20 Points Between the following two circuits a 10 Points if E is the latest arriving signal which circuit is preferred in case of speed b 10 Points which circuit has longer worst case rising propagation delay How about falling propagation delay Consider the internal capacitances Assume both are driving the same capacitive load 7 20 Points a 10 Points Implement the function X A B C D E F G using minimal number of transistors b 5 Points Size the transistors so that the output resistance is the same as an inverter with Wp 2Wn c 10 Points What is the ratio of best and worst case rising delay How about falling delay Ignoring internal capacitance 8 25 Points a 5 Points What logic function does the circuit below implements Size the transistors such that the output resistance is the same as an inverter with Wp 4Wn b 10 Points What are the input patterns that give the worst case tpHL and tpLH State clearly what are the initial input patterns and which input s has to make a transition in order to achieve this maximum propagation delay Consider the effect of the capacitances at the internal nodes c 10 Points If P A 1 0 5 P B 1 0 2 P C 1 0 3 and P D 1 1 determine the power dissipation in the logic gate Assume VDD 2 5V Cout 30fF and fclk 250MHz 9 25 Points Consider a pseudo NMOS inverter Use the following parameter values for calculation VDD 1V Vtn Vtp 0 3V kp pcox 30 A V2 kn ncox 60 A V2 Wn Ln 2 Wp Lp 1 0 Calculate the noise margin of this pseudo NMOS inverter EE577A Homework 0 Spring 2014 Shahin Nazarian 10 100 Points The picture below shows the layout of a circuit a 10 Points Draw the transistor level of schematic of this circuit b 10 Points Plot the truth table of this circuit i1 and i2 are inputs o1 and o2 are outputs c 5 Points What is the function of this circuit d 5 Points If the circle in the picture is shorted to Vdd due to manufacturing defect what would the circuit behave e 10 Points Assuming step waveform for the input signal calculate the propagation delay for the i rising output and ii falling output using average current method f 10 Points Repeat the previous part using the differential equation method g 10 Points Using the results of previous part s calculate an equivalent ohmic resistance for the NMOS and PMOS transistors to model their resistive behavior during falling and rising output h 10 Points Assuming a more realistic input signal with rise and fall times of 100ps and 120ps adjust the propagation delay for the falling and rising output calculated in part b i 15 Points Calculate the rise time based on 30 to 70 VDD crossing points using the average current method only j 15 Points Calculate the fall time based on 85 to 15 VDD crossing points using the average current method only EE577A Homework 0 Spring 2014 Shahin Nazarian