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X-Tolerant Test Response Compaction

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Special ITC Section5660740-7475/05/$20.00 © 2005 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of ComputersDIGITAL CIRCUIT TESTINGinvolves applying testpatterns and observing the circuit’s responses to theapplied patterns. The tester compares the observedresponse to a test pattern with the expected response anddeclares a chip defective upon mismatch. Test engineersusually obtain the expected response through fault-freesimulation of the circuit for the corresponding test pat-tern. Unfortunately, fault-free simulation cannot alwaysdetermine the expected response to be 0 or 1. In thatcase, the expected response is an unknown, or X. Ofcourse, an actual defect-free or defective chip will pro-duce 0 or 1; however, because the simulated expectedresponse is X, we cannot compare the actual chip’sresponse with a golden reference. Hence, this testresponse is ignored during testing. Table 1 explains test-ing in the presence of Xs.Table 2 summarizes the major sources of Xs intoday’s designs. Proper DFT techniques must beemployed to minimize Xs. However, it is impractical toeliminate all X sources due to timing constraints, areaoverhead, simulation engine inefficiencies (such as 0-delay simulation), and inaccuracies in modeling thebehaviors of certain memory, custom logic, and analogcircuit blocks (also called black boxes). Some of theseproblems become visible very late in design or after ICmanufacture, when it is difficult or impossible to insertadditional DFT structures. Table 3 showsfour industrial ASIC designs with theircorresponding X densities—the percent-age of response bits whose expected val-ues are Xs.For designs with traditional scan DFT,handling Xs in test responses is simple—the tester ignores expected test responsebits with Xs. However, the presence of Xsposes a major challenge for designs using test compres-sion1and BIST. For example, consider the use of classi-cal signature analyzers, such as multiple-input signatureregisters (MISRs), for response compaction. Figure 1 (p.568) shows an example. The outputs of four scan chainsare connected to the MISR inputs. The initial MISR stateis 0000. The figure shows the MISR states during the firstfour clock cycles. Xs appearing at scan chain outputscorrupt the MISR contents. After four clock cycles, theexpected MISR signature obtained from fault-free simu-lation consists entirely of Xs. The tester ignores signaturebits whose expected values are Xs during comparison ofthe expected signature with the actual signature. In thisexample, no comparison can be made.Any response compaction technique must be able todetect a defective chip in the presence of residual Xs thatneither DFT nor accurate modeling can eliminate. Thisarticle presents an overview of response compactordesign techniques that we have developed.2-4Theseresponse compactors tolerate the presence of Xs withpractically no impact on test quality. Depending on thenumber of Xs in a design, they can reduce test responsedata volume by up to three orders of magnitude, as sup-ported by data from actual designs. No assumptionsabout defect behaviors are necessary. For example, it isnot necessary to assume that all defects behave as sin-X-Tolerant Test ResponseCompactionEditor’s note:Larger, denser designs lead to more defects; higher quality requirements andnew test methods lead to an explosion in test data volume. Test compressiontechniques attempt to do more testing with fewer bits. This article summarizesone such method, X-compact, which addresses how unknowns, the bane ofcompression and logic BIST techniques, are eliminated.—Scott Davidson, Sun MicrosystemsSubhasish MitraIntelSteven S. LumettaUniversity of Illinois at Urbana-ChampaignMichael MitzenmacherHarvard UniversityNishant PatilIntelgle stuck-at faults. Moreover, engineeringchange orders or test pattern changesafter tapeout do not affect the responsecompaction hardware.Two major types of techniques for testresponse compaction in the presence ofXs have appeared in the literature: fixingthe Xs as 0s and 1s before they enter thecompaction hardware,5-9and postpro-cessing response data to determinewhether the tested IC is defective.10Theseapproaches require significant tester sup-port or knowledge of the exact positionsof Xs in test responses, or both. Some ofthese techniques mask the outputs ofentire scan chains, significantly affectingtest quality in terms of defect coverage(not necessarily fault coverage). The X tol-erance approach we describe here comesfrom the original X-compact idea(described in the next section) andimposes no such requirements, makes noassumptions about defect behaviors, andis ideal for BIST and test compression.Previous publications present a moredetailed discussion of the benefits of theseX-tolerant response compactors overother response compaction techniques.3,4Of course, other techniques and tester fea-tures can complement our technique.X-tolerant responsecompaction theorySuppose that n test response bits arecompacted into m bits, m < n. We repre-sent this situation with a matrix composedof n rows and m columns. Each row rep-resents a bit in the uncompacted testresponse, and each column represents abit in the compacted test response. Thematrix entry corresponding to row i andcolumn j is 1, if and only if bit j of the com-pacted test response depends on bit i ofthe uncompacted test response. Other-wise, the entry is 0. This matrix is called anX-compact matrix. We obtain a bit in thecompacted response by calculating theXOR of bits in the uncompacted testresponse that have 1s in the compactedresponse bit’s column.567November–December 2005Table 1. Testing in the presence of Xs. Responses Expected Actual Test Test pattern (simulated) (silicon) resultPattern 1: The chip passes this 0 0 Passtest pattern since all response 1 1 Passbits are either ignored or pass. X 1 Ignore1 1 PassX 0 IgnorePattern 2: The chip fails this 0 0 Passpattern since there is one 1 0 Failresponse bit that is not X 0 Ignoreignored and does not match 1 1 Passthe expected value. X 1 IgnoreTable 2. Major sources of Xs.X sources Explanation Fixed by DFT?Uninitialized bistables Initial state unknown Yes, with initialization circuitryBus contention, Multiple bus drivers enabled Yes, with ATPG constraints floating buses or all bus drivers disabled or test pointsBlack boxes Structures for which creating Sometimes, with isolation accurate digital-logic models collars;


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