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X-Tolerant Test Response Compaction



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Special ITC Section X Tolerant Test Response Compaction Subhasish Mitra Michael Mitzenmacher Intel Harvard University Steven S Lumetta Nishant Patil University of Illinois at Urbana Champaign Intel additional DFT structures Table 3 shows four industrial ASIC designs with their corresponding X densities the percentage of response bits whose expected values are Xs For designs with traditional scan DFT handling Xs in test responses is simple the tester ignores expected test response bits with Xs However the presence of Xs poses a major challenge for designs using test compression1 and BIST For example consider the use of classical signature analyzers such as multiple input signature registers MISRs for response compaction Figure 1 p 568 shows an example The outputs of four scan chains are connected to the MISR inputs The initial MISR state is 0000 The gure shows the MISR states during the rst four clock cycles Xs appearing at scan chain outputs corrupt the MISR contents After four clock cycles the expected MISR signature obtained from fault free simulation consists entirely of Xs The tester ignores signature bits whose expected values are Xs during comparison of the expected signature with the actual signature In this example no comparison can be made Any response compaction technique must be able to detect a defective chip in the presence of residual Xs that neither DFT nor accurate modeling can eliminate This article presents an overview of response compactor design techniques that we have developed 2 4 These response compactors tolerate the presence of Xs with practically no impact on test quality Depending on the number of Xs in a design they can reduce test response data volume by up to three orders of magnitude as supported by data from actual designs No assumptions about defect behaviors are necessary For example it is not necessary to assume that all defects behave as sin Editor s note Larger denser designs lead to more defects higher quality requirements and



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