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SJSU EE 270 - Review of VHDL

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Authored by Dr. Tri Caohuu& Vivek Verma 1Review of VHDLz Introduction z The Five Design Unitsz Modeling Stylesz Concurrent/Sequential StatementsAuthored by Dr. Tri Caohuu& Vivek VermaDr. Tri Caohuu © 2006 Andy DavisLecture 2 2What is VHDL?z VHSIC (Very High Speed Integrated Circuit) Hardware DescriptionLanguagez VHDL is a “description” language, not a programminglanguage like C, Pascal, Java.z Originally developed for Department of Defense, first releasedin 1985 as an IEEE standard, last major revision IEEE Std 1076-1993z Enjoys industry wide acceptance – Intel, IBM, SunMicrosystems, NEC, Synopsys, Cadence, etc.z Not technology specific but predominantly used for digitalsystem designz Primary uses are for design verification through simulation anddesign creation through synthesisAuthored by Dr. Tri Caohuu& Vivek VermaDr. Tri Caohuu © 2006 Andy DavisLecture 2 3VHDL Capabilitiesz Exchange medium between chip vendors and CAD tool usersz Supports a wide range of abstraction levels, design, modeling stylesa. Behavioralb. Dataflowc. Structurald. Mixedz Clear separation of component’s architecture and interfacez Supports both synchronous and asynchronous timing modelsz Various delay constraints can be describedz Allows defining new data typesz Supports parameterized design using generics and attributesz Is case insensitive and a strongly typed languagez IEEE and ANSI Standard, therefore very portableAuthored by Dr. Tri Caohuu& Vivek VermaDr. Tri Caohuu © 2006 Andy DavisLecture 2 4VHDL Primary ConstructsVHDL has five primary design constructs, also known as “Design Units”, used to describe logic1. EntityThe interface of a logic circuit is represented by entity2. ArchitectureArchitecture describes a particular implementation of anentity3. ConfigurationConfiguration binds entities, architectures, andcomponent declarations4. Package declarationPackage allows a convenient way to define and groupfunctions, procedures, types, components, etc.5. Package bodyPackage body contains the implementation of thefunctionality exposed by package declarationAuthored by Dr. Tri Caohuu& Vivek VermaDr. Tri Caohuu © 2006 Andy DavisLecture 2 5Design Unit : Entityz Entity defines the interface of the hardware moduleto the outside environment in which it is usedz Entity declaration syntax structure is as followsPort is used to pass the declared signals to and from external designGeneric is used to pass parameters from higher level design to the modulez ExampleAuthored by Dr. Tri Caohuu& Vivek VermaDr. Tri Caohuu © 2006 Andy DavisLecture 2 6Design Unit : Architecturez Architecture is the functionality description of thesystem declared by the entityz It can be a behavioral description or it can be astructural decomposition of the body in terms ofsimpler componentsz An architecture/entity pair defines a circuit. Multiplearchitectures can be defined for an entitysignal are any internal signals to be generated inside the modulecomponent is used for declaring any external entities to be used in this moduledescription can be either behavioral or structuralAuthored by Dr. Tri Caohuu& Vivek VermaDr. Tri Caohuu © 2006 Andy DavisLecture 2 7Design Unit : Architecturez Exampletemp is a declared signal , a, b, cin, sum, cout are port signalsP1, P2, P3 are optional implicit process labelsAuthored by Dr. Tri Caohuu& Vivek VermaDr. Tri Caohuu © 2006 Andy DavisLecture 2 8Design Unit : Configurationz Serves two purposesz Used to bind an architecture to an entityz Used to bind an entity to a component declarationz Configuration specification must be placed inside thearchitecture bodyz Configuration syntax structure is as followsuse clauses are for binding an entity/architecture or an entity/component pairfor…end for are for defining configuration block specifications, not be confused with forloopsAuthored by Dr. Tri Caohuu& Vivek VermaDr. Tri Caohuu © 2006 Andy DavisLecture 2 9Design Unit : Configurationz ExampleX1 is an instantiation of component XOR2 being bound to entity CMOS_Lib.XOR_gatewhich is in turn being bound to architecture DataflowX2 is an instantiation of component XOR2 being bound to another configuration thatbinds entity XOR2 with an architectureIf X1 and X2 were both being bound to the same entity, then you could just sayfor all : XOR2 use entity some_entity (architecture)Authored by Dr. Tri Caohuu& Vivek VermaDr. Tri Caohuu © 2006 Andy DavisLecture 2 10Design Unit : Package Declarationz Packages are used to store commonly referenced types,functions, procedures, resolution functions, or componentsz Package declaration may only define the visible contents of thepackagez ExampleAuthored by Dr. Tri Caohuu& Vivek VermaDr. Tri Caohuu © 2006 Andy DavisLecture 2 11Design Unit : Package Bodyz The package body is essentially a listing of the implementationsfor functionality exposed by the package declarationz ExampleAuthored by Dr. Tri Caohuu& Vivek VermaDr. Tri Caohuu © 2006 Andy DavisLecture 2 12VHDL Modeling StylesCommonly used modeling styles in hardwaredescription arez Structural – Circuit is described as a network of interconnectedcomponentsz Behavioral – Circuit is described as an i/o relationshipusing sequential statements inside a processz Dataflow – Circuit is described using concurrent statementsz Mixed - This style of modeling uses any combination ofother stylesAuthored by Dr. Tri Caohuu& Vivek VermaDr. Tri Caohuu © 2006 Andy DavisLecture 2 13VHDL Modeling Styles : Structuralz Focus is on how components are interconnected rather than theoperation of each fundamental component.z Three features of a structural description1. Ability to define a list of components2. Definition of signals to interconnect these components3. Ability to distinguish between multiple copies of samecomponent using labelsz ExampleAuthored by Dr. Tri Caohuu& Vivek VermaDr. Tri Caohuu © 2006 Andy DavisLecture 2 14VHDL Modeling Styles : Behavioralz This style describes a behavior in a “program-like” (procedural)manner, using the process constructs provided in VHDLz Multiple process statements can be used to describe concurrencyz Notice the following


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