ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design PracticesPrev…Adders/SubtractorsHalf Adder: adds two 1-bit operandsFull Adders: provide for carries between bit positionsSlide 6Slide 7Full-adder circuitSlide 9Slide 10Ripple adder74x283 4-bit adder16-bit group-ripple adderSubtractionFull Subtractor = full adder, almostSlide 16Using Adder as a SubtractorSlide 18MSI Arithmetic Logic Units (ALU )Chapter SummaryChapter SummaryNext…ECE 3110: Introduction to Digital SystemsChapter 6 Combinational Logic Design PracticesAdders, subtractors, ALUsPrev…XOR (2-level, 3-level)Equivalent symbolsXNORParity Circuits (Odd, even)Daisy chainTreeComparatorsIterativeParallelAdders/SubtractorsHalf AdderFull AdderRipple AdderFull SubtractorRipple SubtractorAdder/ Subtractor CircuitHalf Adder: adds two 1-bit operandsTruth table :X Y HS=(X+Y) CO0 0 0 00 1 1 01 0 1 01 1 0 1 Y X H S COYXHS YXCO -Full Adders: provide for carries between bit positionsBasic building block is “full adder”1-bit-wide adder, produces sum and carry outputsTruth table:Full Adders: provide for carries between bit positionsBasic building block is “full adder”1-bit-wide adder, produces sum and carry outputsTruth table:X Y Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1Full Adders: provide for carries between bit positionsBasic building block is “full adder”1-bit-wide adder, produces sum and carry outputsTruth table:X Y Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1S is 1 if an odd number of inputs are 1.COUT is 1 if two or more of the inputs are 1.Recall: Table 2-3, pp32Full-adder circuitFull-adder circuitFull-adder circuitRipple adderSpeed limited by carry chainFaster adders eliminate or limit carry chain2-level AND-OR logic ==> 2n product terms3 or 4 levels of logic, carry look-ahead74x2834-bit adderUses carry look-ahead internally16-bit group-ripple adderSubtractionSubtraction is the same as addition of the two’s complement.The two’s complement is the bit-by-bit complement plus 1.Therefore, X – Y = X + Y’ + 1Full Subtractor = full adder, almostX,Y are n-bit unsigned binary numbersAddition : S = X + YSubtraction : D = X - Y = X + (-Y) = = X+ (Two’s Complement of Y) = X+ (One’s Complement of Y) + 1 = X+ Y’+ 1Full Subtractor = full adder, almostX,Y are n-bit unsigned binary numbersAddition : S = X + YSubtraction : D = X - Y = X + (-Y) = = X+ (Two’s Complement of Y) = X+ (One’s Complement of Y) + 1 = X+ Y’+ 1Using Adder as a SubtractorRipple Adder can be used as a Subtractor by inverting Y and setting the initial carry ( CIN ) to 1Using Adder as a SubtractorRipple Adder can be used as a Subtractor by inverting Y and setting the initial carry ( CIN ) to 1MSI Arithmetic Logic Units (ALU )ALU performs Arithmetic and Logical Functions - A , B : 4 bits inputs- S3,S2,S1,S0 : Function select- M=0 : Arithmetic operations +=Plus , - = Minus M=1 : Logical operations : += OR , . =ANDExample : Inputs FunctionsS3 S2 S1 S0 M=0 M=10 0 0 0 F= A-1+CIN F=A’0 1 1 0 F= A-B-1+CIN F=A XOR B’1 0 0 1 F= A+B+CIN F=A XOR B1 0 1 1 F=(A OR B)+ CIN F=A+B1 1 0 0 F= A+A+CIN F= 00001 1 1 1 F=A+CIN F=AS1S2S3F1F2MCINA0S0 F0B074x181F3COUTA1B1A2B2A3B3 A=BPGChapter Summary Documentation Standards:- Gate symbols, Signals Active Levels, Bubble to Bubble Logic- Block diagram, Schematic Diagram, Timing Diagram.Combinational Logic design Structures:1-Decoders : Binary Decoders, Cascading decoders2-Encoders : Binary Encoder, Priority Encoder, Cascading Encoders, Encoder applications.3-Three State Buffers : SSI buffers, MSI Octal Buffer , Octal Three-state TransceiverChapter Summary4- Multiplexers : MUX operation, Single/Multiple outputs MUX, Expanding MUXs5- Demultiplexers : MUX/DMUX operation, Using Decoders as Demultiplexers.6- XOR and XNOR Gates: Logic Symbols, Equivalent Symbols, Parity Circuits, Parity Circuit application ( memory unit checking )7- Comparators : Parallel Comparators, Iterative Comparators, Cascading Comparators8-Adders : Half Adder, Full Adder, Ripple Adder, Subtractor, Ripple Adder / Subtractor Unit, 9- Arithmetic Logic UnitsNext…ProjectReading Wakerly
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