TnTech ECE 3110 - Combinational Logic Design Practices

Unformatted text preview:

ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design PracticesPrev…Adders/SubtractorsHalf Adder: adds two 1-bit operandsFull Adders: provide for carries between bit positionsSlide 6Slide 7Full-adder circuitSlide 9Slide 10Ripple adder74x283 4-bit adder16-bit group-ripple adderSubtractionFull Subtractor = full adder, almostSlide 16Using Adder as a SubtractorSlide 18MSI Arithmetic Logic Units (ALU )Chapter SummaryChapter SummaryNext…ECE 3110: Introduction to Digital SystemsChapter 6 Combinational Logic Design PracticesAdders, subtractors, ALUsPrev…XOR (2-level, 3-level)Equivalent symbolsXNORParity Circuits (Odd, even)Daisy chainTreeComparatorsIterativeParallelAdders/SubtractorsHalf AdderFull AdderRipple AdderFull SubtractorRipple SubtractorAdder/ Subtractor CircuitHalf Adder: adds two 1-bit operandsTruth table :X Y HS=(X+Y) CO0 0 0 00 1 1 01 0 1 01 1 0 1  Y X H S COYXHS YXCO -Full Adders: provide for carries between bit positionsBasic building block is “full adder”1-bit-wide adder, produces sum and carry outputsTruth table:Full Adders: provide for carries between bit positionsBasic building block is “full adder”1-bit-wide adder, produces sum and carry outputsTruth table:X Y Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1Full Adders: provide for carries between bit positionsBasic building block is “full adder”1-bit-wide adder, produces sum and carry outputsTruth table:X Y Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1S is 1 if an odd number of inputs are 1.COUT is 1 if two or more of the inputs are 1.Recall: Table 2-3, pp32Full-adder circuitFull-adder circuitFull-adder circuitRipple adderSpeed limited by carry chainFaster adders eliminate or limit carry chain2-level AND-OR logic ==> 2n product terms3 or 4 levels of logic, carry look-ahead74x2834-bit adderUses carry look-ahead internally16-bit group-ripple adderSubtractionSubtraction is the same as addition of the two’s complement.The two’s complement is the bit-by-bit complement plus 1.Therefore, X – Y = X + Y’ + 1Full Subtractor = full adder, almostX,Y are n-bit unsigned binary numbersAddition : S = X + YSubtraction : D = X - Y = X + (-Y) = = X+ (Two’s Complement of Y) = X+ (One’s Complement of Y) + 1 = X+ Y’+ 1Full Subtractor = full adder, almostX,Y are n-bit unsigned binary numbersAddition : S = X + YSubtraction : D = X - Y = X + (-Y) = = X+ (Two’s Complement of Y) = X+ (One’s Complement of Y) + 1 = X+ Y’+ 1Using Adder as a SubtractorRipple Adder can be used as a Subtractor by inverting Y and setting the initial carry ( CIN ) to 1Using Adder as a SubtractorRipple Adder can be used as a Subtractor by inverting Y and setting the initial carry ( CIN ) to 1MSI Arithmetic Logic Units (ALU )ALU performs Arithmetic and Logical Functions - A , B : 4 bits inputs- S3,S2,S1,S0 : Function select- M=0 : Arithmetic operations +=Plus , - = Minus M=1 : Logical operations : += OR , . =ANDExample : Inputs FunctionsS3 S2 S1 S0 M=0 M=10 0 0 0 F= A-1+CIN F=A’0 1 1 0 F= A-B-1+CIN F=A XOR B’1 0 0 1 F= A+B+CIN F=A XOR B1 0 1 1 F=(A OR B)+ CIN F=A+B1 1 0 0 F= A+A+CIN F= 00001 1 1 1 F=A+CIN F=AS1S2S3F1F2MCINA0S0 F0B074x181F3COUTA1B1A2B2A3B3 A=BPGChapter Summary Documentation Standards:- Gate symbols, Signals Active Levels, Bubble to Bubble Logic- Block diagram, Schematic Diagram, Timing Diagram.Combinational Logic design Structures:1-Decoders : Binary Decoders, Cascading decoders2-Encoders : Binary Encoder, Priority Encoder, Cascading Encoders, Encoder applications.3-Three State Buffers : SSI buffers, MSI Octal Buffer , Octal Three-state TransceiverChapter Summary4- Multiplexers : MUX operation, Single/Multiple outputs MUX, Expanding MUXs5- Demultiplexers : MUX/DMUX operation, Using Decoders as Demultiplexers.6- XOR and XNOR Gates: Logic Symbols, Equivalent Symbols, Parity Circuits, Parity Circuit application ( memory unit checking )7- Comparators : Parallel Comparators, Iterative Comparators, Cascading Comparators8-Adders : Half Adder, Full Adder, Ripple Adder, Subtractor, Ripple Adder / Subtractor Unit, 9- Arithmetic Logic UnitsNext…ProjectReading Wakerly


View Full Document

TnTech ECE 3110 - Combinational Logic Design Practices

Download Combinational Logic Design Practices
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Combinational Logic Design Practices and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Combinational Logic Design Practices 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?