EECS 242 Active Technology for Communication Circuits UC Berkeley EECS 242 Copyright Prof Ali M Niknejad Outline Comparison of technology choices for communication circuits Si npn Si NMOS SiGe HBT CMOS JFETs MESFETs Key metrics Large signal relations Small signal models UC Berkeley EECS 242 2 Copyright Prof Ali M Niknejad Generic Three Terminal Device Io Vi Vo Output current is dependent on input voltage Examples npn BJT n ch JFET NMOS GaAs MESFET vacuum tube Emerging Technologies SOI Multi Gate FETs FinFETs CNT Nanowire UC Berkeley EECS 242 3 Copyright Prof Ali M Niknejad Large Signal Equations Bipolar forward active JFET MESFET pinch off regime MOSFET saturation Vacuum Tube UC Berkeley EECS 242 4 Copyright Prof Ali M Niknejad Generic Device Behavior non linear resistor region constant current resistor region slope is output resistance of device UC Berkeley EECS 242 5 Copyright Prof Ali M Niknejad Large Signal Models Resistors and capacitors are non linear R and Ro depend on bias point Rg intrinsic depends on channel inversion level Rb can change due to current spreading effects Cgs varies from accumulation to depletion to inversion Junction capacitors vary with bias UC Berkeley EECS 242 6 Copyright Prof Ali M Niknejad Small Signal Models In small signal regime R C linear about a bias point For BJT rx rb UC Berkeley EECS 242 For a FET input 7 Copyright Prof Ali M Niknejad Various Figures of Merit Intrinsic Voltage Gain a0 Power Gain Unilateral Gain Noise Noise figure NF and M Noise Measure Flicker noise corner frequency Unity Gain Frequency fT Maximum Osc Freq fmax Gain normalized to current gm I Gain Bandwidth fT gm I UC Berkeley EECS 242 8 Copyright Prof Ali M Niknejad Other Important Metrics Complementary devices Device with same order of magnitude of fT fmax Lateral pnp a dog compared to vertical npn Availability of Logic Low power high density Useful with S H sample hold and SC switch capacitor circuits Important for calibration Breakdown voltage Power amplifiers dynamic range of analog circuitry Thermal conductivity Power amplifiers Quality and precision of passives Inductors capacitors resistors and transmission lines UC Berkeley EECS 242 9 Copyright Prof Ali M Niknejad Device Current Gain H parameters Current gain UC Berkeley EECS 242 10 Copyright Prof Ali M Niknejad BJT Cross Section Most transistor action occurs in the small npn sandwich under the emitter The base width should be made as small as possible in order to minimize recombination The emitter doping should be much larger than the base doping to maximize electron injection into the base A SiGe HBT transistor behaves very similarly to a normal BJT but has lower base resistance rb since the doping in the base can be increased without compromising performance of the structure UC Berkeley EECS 242 11 Copyright Prof Ali M Niknejad Bipolar Small Signal Model The resistor R dominates the input impedance at low frequency At high frequency though C dominates C is due to the collector base reverse biased diode capacitance Ccs is the collector to substrate parasitic capacitance In some processes this is reduced with an oxide layer C has two components due to the junction capacitance forward biased and a diffusion capacitance UC Berkeley EECS 242 12 Copyright Prof Ali M Niknejad Bipolar Exponential Due to Boltzmann statistics the collector current is described very accurately with an exponential relationship The device transconductance is therefore proportional to current where kT q 26mV at room temperature Compare this to the equation for the FET Since we usually have kT q Vgs VT the bipolar has a much larger transconductance for the same current This is the biggest advantage of a bipolar over a FET UC Berkeley EECS 242 13 Copyright Prof Ali M Niknejad Control Terminal Sensitivity BJT 10 IC IC MOSFET UC Berkeley EECS 242 14 Copyright Prof Ali M Niknejad Bipolar Unity Gain Frequency The unity gain frequency of the BJT device is given by where we assumed the forward bias junction has Cje 2 Cje0 Since the base collector junction capacitance C is a function of reverse bias we should bias the collector voltage as high as possible for best performance The diffusion capacitance is a function of collector current UC Berkeley EECS 242 15 Copyright Prof Ali M Niknejad Bipolar Optimum Bias Point We can clearly see that if we continue to increase IC then gm IC increases and the limiting value of fT is given by the forward transit time In practice though we find that there is an optimum collector current Beyond this current the transit time increases This optimum point occurs due to the Kirk Effect It s related to the base widening due to high level injection Not Star Trek UC Berkeley EECS 242 16 Copyright Prof Ali M Niknejad BJT Base Transit Time E B C n n p WB RB Base transit time Current gain unity freq n n buried layer p substrate UC Berkeley EECS 242 17 Copyright Prof Ali M Niknejad CMOS Cross Section Modern CMOS process has very short channel lengths L 100 nm To ensure gate control of channel as opposed to drain control DIBL we employ thin junctions and thin oxide tox 5 nm Due to lithographic limitations there is an overlap between the gate and the source drain junctions This leads to overlap capacitance In a modern FET this is a substantial fraction of the gate capacitance up to half UC Berkeley EECS 242 18 Copyright Prof Ali M Niknejad FET Small Signal Model The junctions of a FET form reverse biased pn junctions with the substrate well or the body node This is another form of parasitic capacitance in the structure Cdb and Csb At DC input is an open circuit The input impedance has a small real part due to the gate resistance Rg polysilicon gate and NQS and Rs d account for junction and contact resistance In the forward active saturation region the input capacitance is given by Cgs Ro is due to channel length modulation and other short channel effects such as DIBL UC Berkeley EECS 242 19 Copyright Prof Ali M Niknejad FET Simplified Models For low frequencies the resistors are ignored But these resistors play an important role at high frequencies If the source is tied to the bulk then the model simplifies a lot more Don t forget that layout parasitics increase the capacitance in the model sometimes substantially esp in deep submicron technologies UC Berkeley EECS 242 20 Copyright Prof Ali M Niknejad FET Unity Gain Frequency Long channel FET Note that there is a peak fT since eventually the mobility of the transistor drops due