Lecture 2 ECEN 4517 5517 Experiment 1 Photovoltaic System Characterize the SQ 85 PV panels and find numerical values of model parameters for use now and later in semester Test the inverter provided Charge the battery from the panel using the Direct Energy Transfer method Hope for sun Experiment 1 to be performed this week weather permitting Final report for Exp 1 due at beginning of lab on Jan 26 28 ECEN 4517 1 Photovoltaic cell model Rs ID I0 D Ipv Ipv ISC VD Rp Vpv PV cell characteristic Increasing I0 PPT Vpk Ipk VOC Vpv Find these parameters I0 Photogenerated current proportional to solar irradiation estimate constant having units of A W m2 IDSS Exponential diode characteristic related to VOC Rp Shunt resistance typically large Rs Series resistance typically small ECEN 4517 4 Shell Solar SQ 85 panel 18 cells in series 36 series connected PV cells 2 backplane diodes 85 W at 1000 W m2 18 cells in series IPV Power Electronics Laboratory VPV Apparent path of sun through sky Baseline Rd is 40 N Times are not corrected for location of Boulder in Mountain Time Zone Net panel irradiation depends on cos with angle between panel direction and direction to sun So take your data quickly ECEN 4517 5 Laboratory facilities mobile PV cart Inverter 60 Hz 300 W 120 Vrms 17 2 V at 4 95 A Shell SQ 85P 6 outlet ac power strip PV panel Battery 12 V deep discharge 56 A hr Alarm Battery low voltage Voltmeter Battery voltage Battery Connectors PV panel 85 Wpk 12V Battery charger 12V Off cart on stationary workbench 5V 8 Isolated dc dc converters Deep Discharge Lead Acid Batteries Theory and modeling of batteries Don t overcharge this causes outgassing and can quickly ruin the battery Don t discharge below 50 SOC this reduces battery life 56 Ampere hour Battery state of charge SOC vs terminal voltage 100 SOC 12 80 volts or greater 75 SOC 12 55 volts 50 SOC 12 20 volts 25 SOC 11 75 volts 0 SOC 10 50 volts 9 Lab reports One report per group Include names of every group member on first page of report Report all data from every step of procedure and calculations Adequately document each step Discuss every step of procedure and calculations Interpret the data It is your job to convince the grader that you understand what is going on with every step Regurgitating the data with no discussion or interpretation will not yield very many points Concise is good ECEN 4517 2 Upcoming due dates Experiment 1 Final report due at beginning of lab session next week Jan 26 28 Experiment 3 Prelab assignment dc dc converter design for MPPT due at beginning of lecture in two weeks Feb 2 ECEN 4517 4 Upcoming weeks Design and build MPPT system Exp 3 DC DC converter Exp 2 introduction to MSP430 microcontroller ECEN 4517 3 Experiment 2 Introduction to MSP 430F2616 Microcontroller ECEN 4517 7 Microcontroller Pinouts ADC inputs Timer B outputs to LED ECEN 4517 8 Microcontroller default settings Upon power on reset POR the MSP430F2616 comes up with the following conditions Watchdog timer is enabled All pins are set to read state Processor internal clock is set to 1 2 MHz ECEN 4517 9 Peripherals are controlled by registers in addressable memory Example Port P5 comprised of eight pins labeled P5 0 P5 7 C code variable name Register name Address TI provides a header file that sets up all registers with C code variable names assigned to the correct addresses so you don t have to worry about it Just add the following statement to the beginning of your C code include msp430x26x h This file also defines constants that are useful for setting peripheral functions ECEN 4517 10 Examples Configure pin P3 0 to be a digital output and toggle its value P3DIR 0x01 P3OUT 0x01 OR the contents of register P3DIR with hex 01 forcing the first bit high This configures pin P3 0 to be an output EXOR the contents of P3OUT with hex 01 toggling the first bit This changes the state of logic output P3 0 Turn off the watchdog timer WDTCTL WDTPW WDTHOLD ECEN 4517 Sets the WDT control register to disable the watchdog timer function 11 C code to toggle pin P3 0 include msp430x26x h void main void WDTCTL WDTPW WDTHOLD P3DIR 0x01 for volatile unsigned int i P3OUT 0x01 i 10000 do i while i 0 ECEN 4517 Stop watchdog timer Configure pin P3 0 to output direction infinite loop Toggle P3 0 output Wait 10000 counts 12 Setting the processor internal clock frequency The processor contains a digitally controlled oscillator DCO whose frequency can be programmed The power on default frequency is 1 2 MHz The following commands set the frequency to the maximum 16 20 MHz BCSCTL1 RSEL0 RSEL1 RSEL2 RSEL3 DCOCTL DCO0 DCO1 DCO2 ECEN 4517 13 Operation of Timer B as a PWM See MSP430x2xx Family User Guide Chapter 13 Timer B includes One timer block with 16 bit counter Seven capture compare registers Use one CCR to set switching frequency fs DCO freq count Use other CCR s to set duty cycles Can control up to six independent output duty cycles Need to configure Timer B and write values to set fs and duty cycle s ECEN 4517 14 Timer B control registers C code variable name Address Register name ECEN 4517 15 Timer B Control Register TBCTL See MSP430x2xx Family User Guide Chapter 13 p 13 21 C code TBCTL TBSSEL2 MC2 This sets the Timer B clock source to SMCLK derived from processor clock DCO and sets the mode to Continuous mode TBSSEL2 and MC2 are constants defined in the standard header file The timer is in Stop mode at POR and starts counting when this statement is executed ECEN 4517 17 Example Configuring Timer B as a PWM include msp430x26x h void main void WDTCTL WDTPW WDTHOLD BCSCTL1 RSEL0 RSEL1 RSEL2 RSEL3 DCOCTL DCO0 DCO1 DCO2 P4DIR 0x7e P4SEL 0x7e TBCCR0 200 TBCCTL1 OUTMOD 7 TBCCR1 150 TBCCTL2 OUTMOD 3 TBCCR2 150 TBCCTL3 OUTMOD 3 TBCCR3 30 TBCTL TBSSEL 2 MC 1 for ECEN 4517 16 Stop WDT Set processor DCO to max P4 1 P4 6 output P4 1 P4 6 TBx options PWM freq 20 MHz 200 CCR1 reset set mode CCR1 duty cycle 150 200 CCR2 set reset mode CCR2 duty cycle 150 200 CCR3 set reset mode CCR3 duty cycle 30 200 use SMCLK up mode The MSP 430 board in kits R4 R3 DNP MSP430F2616 DNP 0V R5 0 VDD 7 FEEDBACK VTAP 6 VDD 2 SENSE 3 3V voltage regulator 1 2 J6 CON2 8 IN 0V 0V R2 OUT 1 0 1 3 SHUTDOWN C4 1 uF 4 GND 0V ERR 5 C5 10 uF RST U2 LP2951 33 VDD 0V DEBUG INTERFACE VDD VDD R1 47K C1 0 1uF 0V C2 1 uF TDO TDI TMS TCK S1 ALPS SKHUQB056A RST RST C3 2 2 nF 0V 0 0V VDD 1 2 3 J5 CON3 2 1 4 3 6 5 8 7 10 9 11 12 …
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