Spring 2011 Prof. Hyesoon Kim• ARM v7 – Cortex- A, Cortex-R, Cortex-M3, Qualcomm Scorpion• ARM v6 – Cortex-M0, Cortex-M1• ARM v5– ARM7, ARM9, ARM10, StrongARM, Intel XScale• Data processing instructions • Data transfer instructions • Control flow instructionscond 0 0 # opcode S Rn Rd operand 2#rot8-bit immediate#shift sh 0 RmRs sh 1 Rm01031 28 27 26 25 24 21 20 19 16 15 12 11 0 Set condition codes 11 8 7 011 8 7 6 5 4 3 0 11 7 6 5 4 3 0Register shift lengthShift typeSteve Furber, ARM system-on-chip architecture 2ndedition2ndoperand• Using 12 bits how to represent 32-bit immediate value? • Immediate = (0255) x 22n – Where 0≤n≥ 12 (4 bits rotation)– 8 bit immediate + 4-bit shift – 8 bit + 24 = 32 bit representation Steve Furber, ARM system-on-chip architecture 2ndedition• ADD r3, r2, r1, LSL #3; r3:=r2+r1*8• Logical shift vs. Arithmetic shift ?– E.g.) b1011 , Carry:1 – LSL, 1 : b0110 – LSR, 1: b0101– ASL, 1: b0110– ASR, 1: b1101– ROR, 1: b1101– RRX, 1: b1101 carry: 1• Use register to specify shift • ADD r5,r5,r3, LSL r2; r5 := r5+r3 x 2^(r2)Coming from carry bit Input to the ALU Steve Furber, ARM system-on-chip architecture 2ndeditionRegister, optionally with shift operation Shift value can be either be: 5 bit unsigned integer Specified in bottom byte of another register. Used for multiplication by constantImmediate value 8 bit number, with a range of 0-255. Rotated right through even number of positions  Allows increased range of 32-bit constants to be loaded directly into registersResultOperand 1BarrelShifterOperand 2ALU• Consist of :– Arithmetic: ADD ADC SUB SBC RSB RSC– Logical: AND ORR EOR BIC– Comparisons: CMP CMN TST TEQ– Data movement: MOV MVN• These instructions only work on registers, NOT memory.• Syntax:<Operation>{<cond>}{S} Rd, Rn, Operand2• Comparisons set flags only - they do not specify Rd• Data movement does not specify Rn• Second operand is sent to the ALU via barrel shifter.Opcode [24:21]MnemonicMeaningEffect0000ANDLogical bit-wise ANDRd := Rn AND Op20001EORLogical bit-wise exclusive ORRd := Rn EOR Op20010SUBSubtractRd := Rn – Op20011RSBReverse subtractRd: = Op2 – Rn0100ADDAddRd: = Rn + Op20101ADCAdd with carryRd: = Rn + Op2 +C0110SBCSubtract with carryRd: = Rn – Op2 + C-10111RSCReverse subtract with carryRd: = Op2- Rn+C-11000TSTTestScc on Rn AND Op21001TEQTest equivalenceScc on Rn EOR Op21010CMPCompareScc on Rn - Op21011CMNCompare negatedScc on Rn + Op21100ORRLogical bit-wise OrRd: =Rn OR Op21101MOVMoveRd: = Op21110BICBit clearRd: =Rn AND NOT Op21111MVNMove negatedRd: = NOT Op2Steve Furber, ARM system-on-chip architecture 2ndedition• S bit (bit 20)– 1: condition code is set – 0: condition code is unchanged• N: 1: result is negative 0: result is 0 or positive – N = result [31] • Z: 1: zero 0: non-zero • C: Carry-out from ALU when the operation is arithmetic – ADD, ADC, SUB, SBC, RSB, CMP, CMN– Carry out from shifter • V: overflow , non-arithmetic operations do not touch V-bit – Only for signed operationsSteve Furber, ARM system-on-chip architecture 2ndedition• The possible condition codes are listed below:• Note AL is the default and does not need to be specified Not equalUnsigned higher or sameUnsigned lowerMinusEqualOverflowNo overflowUnsigned higherUnsigned lower or samePositive or ZeroLess thanGreater thanLess than or equalAlwaysGreater or equalEQNECS/HSCC/LOPLVSHILSGELTGTLEALMIVCSuffix DescriptionZ=0C=1C=0Z=1Flags testedN=1N=0V=1V=0C=1 & Z=0C=0 or Z=1N=VN!=VZ=0 & N=VZ=1 or N=!VSteve Furber, ARM system-on-chip architecture 2ndedition• 64-bit add with 32-bit operations ADDS r2, r2, r0; 32-bit carry out  CADC r3, r3,r1 ; .. And added into high word R1 R0LSBMSBR3 R2LSBMSB+=R3 R2+CSteve Furber, ARM system-on-chip architecture 2ndedition• Use a sequence of several conditional instructions if (a==0) { a = 1; func(1); }CMP r0,#0 // a == 0MOVEQ r0,#1 // a = 1 BLEQ func // func• Set the flags, then use various condition codesif (a==0) x=0;if (a>0) x=1;CMP r0,#0MOVEQ r1,#0MOVGT r1,#1• Use conditional compare instructionsif (a==4 || a==10) x=0;CMP r0,#4CMPNE r0,#10MOVEQ r1,#0Steve Furber, ARM system-on-chip architecture 2ndedition• Syntax: – MUL{<cond>}{S} Rd, Rm, Rs Rd = Rm * Rs– MLA{<cond>}{S} Rd,Rm,Rs,Rn Rd = (Rm * Rs) + Rn– [U|S]MULL{<cond>}{S} RdLo, RdHi, Rm, Rs RdHi,RdLo := Rm*Rs– [U|S]MLAL{<cond>}{S} RdLo, RdHi, Rm, Rs RdHi,RdLo := (Rm*Rs)+RdHi,RdLo• Cycle time– Basic MUL instruction• 2-5 cycles on ARM7TDMI• 1-3 cycles on StrongARM/XScale• 2 cycles on ARM9E/ARM102xE– +1 cycle for ARM9TDMI (over ARM7TDMI)– +1 cycle for accumulate (not on 9E though result delay is one cycle longer)– +1 cycle for “long”• Above are “general rules” – timing can be vary by architectureOpcode [23:21]MnemonicMeaningEffect000MULMultiply (32-bit result) Rd := (Rm*Rs)[31:0]001MLAMultiply-accumulates (32-bit result)Rd := (Rm*Rs+Rn)[31:0]100UMULLUnsigned multiply longRdHi:RdLo:=Rm*Rs101UMLALUnsigned multiply-accumulate longRdHi:RdLo:+=Rm*Rs110SMULLSigned multiply longRdHi:RdLo:=Rm*Rs111SMLALSigned multiply-accumulate long RdHi:RdLo:+=Rm*Rs• RdHi:RdLo: 64-bit format RdHi: MSB 32 bits, RdLo: LSB 32 bits • N: Rd[31] or RdHi[31]• Z: Rd or RdHi and RdLo are Zero • C: meaningless • V: unchanged• Early ARM supports only 32 bits Multiply operations. 64 bit multiply instructions are supported from ARM7.• Data transfer between registers and memory. • Single word and unsigned byte data transfer instructions• Half-word and signed byte data transfer instructions • Multiple register transfer instructions – Copy subset or multiple registers to memory • Swap memory and register instructions (SWP)• Status register to general register transfer instructionsLDR STR WordLDRB STRB ByteLDRH STRH HalfwordLDRSB Signed byte loadLDRSH Signed halfword load• Memory system must support all access sizes• Syntax:– LDR{<cond>}{<size>} Rd, <address>– STR{<cond>}{<size>} Rd, <address>e.g. LDREQB• Address accessed by LDR/STR is specified by a base register plus an offset• Register indirect memory addressing– LDR r0, [r1] ; r0 := mem32[r1]– STR r0, [r1] ; mem32[r1] := r0• Particular location: – Set base register • an address within 4K bytes of the