First Order IIR Filter using Serial Adder Project for EE166 – spring 2003 San Jose State University ---------------------------------------------------------------------------System ObjectivePowerPoint PresentationSlide 4Slide 5Slide 6Slide 7Slide 8Slide 9TOP LEVELSlide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Control ModuleSlide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30D-FlopSlide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Slide 39Full AdderSlide 41FULL ADDER SCHEMATICHand CalculationsSlide 45Slide 46 Slide 48Slide 49Slide 502to1 MUXMUX2_1 Truth TableSchematicSlide 54Slide 55Slide 56Slide 57LVS reportSlide 59REG ARegister-ASlide 62Slide 63Slide 64Slide 65Slide 66Slide 67REG BRegB SchematicDff SchematicMux SchematicTest BenchWaveformRegB LayoutDRC CheckLVS ReportExtracted WaveformExtracted Propogation TimeBasic Gates1. OR2: Designed the layout for the OR2 gate.Slide 81Slide 82Slide 83Slide 84Slide 85Slide 86Slide 87Slide 88Slide 89Slide 90Slide 91Slide 92Slide 93Slide 94Slide 95First Order IIR Filter using Serial AdderProject for EE166 – spring 2003San Jose State University--------------------------------------------------------------------------- •Meghana Khadkikar•Parul Apan•Rohini Kulkarni•Sidharth Sood•Xiaoya YangSystem ObjectiveInternal Block Diagram of IIRProtocol for receiving input samples• Input samples should be qualified with a load signal (LD_X here)• Samples cannot be accepted faster than once every 6 clock cycles (at 200MHz system CLK, about 33 M samples processed per second)Implementation Targets•System clock = 200 MHz •Total system power <= 0.25 W•Target technology = AMI 0.6u C5N•Output Load of 20 fFDivision of Work•Meghana Khadkikar - REG A, 2to1 MUX, Post extraction Sims, Power Analysis•Parul Apan - Top level integration, Control Module, D-Flop•Rohini Kulkarni - Full Adder•Sidharth Sood - Basic gates•Xiaoya Yang - REG BTOP LEVELTop-Level SchematicImpulse response - inputImpulse response - outputStep response - inputStep response - outputTop-Level - LayoutTop-Level - DRC ReportTop-Level - LVS ReportStep response - Post-extractionImpulse response – Post extractionPower Analysis – Pre ExtractionPower Analysis – Post ExtractionControl ModuleControl ModuleControl Module - SchematicControl moduleControl module - LayoutControl Module - DRCControl module - LVSControl module – Post-extractionD-FlopD-Flop SchematicInitial estimates:-Max setup time ~ 600ps-Clock to Q delay ~ 400ps-Hold time ~ 150psOn this basis, the values for following constants were calculated as:-Ratio = 1.775-Cgin = 10.86 x WN fF (assuming each nand would drive 3 nands)-WN = 2.84u; WP = 4.437uFinal Values:Actual value for ‘Ratio’ was found from parametric analysis keeping WN = 3uIt came out to be 1.8  WP = 5.4uD-Flop CalculationsD-FlopD-Flop- Setup CharacterizationD-Flop LayoutD-Flop DRCD-Flop LVSD-Flop – Post-extractionFull AdderAi Bi Ci Cout Sum0 0 0 0 00 0 1 0 11 0 0 0 11 0 1 1 00 1 0 0 10 1 1 1 01 1 0 1 01 1 1 1 1Truth Table of Full_AdderFULL ADDER SCHEMATICFull Adder -SchematicHand Calculations•AND2:•Tphl=Tplh =1ns•Wn=37u Wp=2.7u ,Wni= 2.7u Wpi=1.5u•OR2•Tphl=Tplh=1ns•Wn=1.5u Wp=2.7u , Wni=2.55u Wpi=4.5u•XOR2:•Tphl=Tplh =1.5ns•Wn=1.65u Wp=3u ,Wni= 2.7u Wpi=1.5u\•Post extraction delay: Tphl=Tplh=1nsFull AdderFull Adder - LayoutFull Adder - DRC•Like matching is enabled.•Net swapping is enabled.•Using terminal names as correspondence points.•Compiling Diva LVS rules...• Net-list summary for /home/sood5306/PROJECT_166/work/rohini/LVS/layout/netlist• count•26 nets•7 terminals•21 pmos•21 nmosLVS reportNet-list summary for /home/sood5306/PROJECT_166/work/rohini/LVS/schematic/netlist count26 nets7 terminals21 pmos21 nmos Terminal correspondence points 1 Ain 2 Bin 3 Cin 4 Cout 5 Sum 6 gnd! 7 vdd!The net-lists match. layout schematicinstancesun-matched 0 0rewired 0 0size errors 0 0pruned 0 0active 42 42total 42 42un-matched 0 0merged 0 0pruned 0 0active 26 26total 26 26terminalsun-matched 0 0matched butdifferent type 2 2total 7 72to1 MUXMUX2_1 Truth TableSEL IN0 IN1 Y0 0 0 00 0 1 00 0 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1Schematic•AOI Implementation•Load was 10fF•Sizing for minimum delay•Wn=3u, Wp=5.4u•Tphl=Tplh=0.5ns•Post Extraction Tphl=Tplh=0.55nsLVS reportNet-list summary for /home/sood5306/PROJECT_166/work/meghana/LVS/schematic/netlist count11 nets6 terminals6 pmos6 nmosTerminal correspondence points 1 IN0 2 IN1 3 SEL 4 Y 5 gnd! 6 vdd!The net-lists match. layout schematicinstancesun-matched 0 0rewired 0 0size errors 0 0pruned 0 0active 12 12total 12 12REG ARegister-A•Register-A is a 4 bit parallel in-serial out register.P3 P2 P1 P0SERIAL_INLOADclkSERIAL_OUT4-bit shift register with parallel loadREG A -SchematicREG A – Transient AnalysisREG A - LayoutREG A - DRCREG A - LVSREG A – Post extractionREG BRegB SchematicGfhDff SchematicRow 1 Row 2 Row 3 Row 4012345678910Main titleColumn 1 Column 2 Column 3Mux SchematicRow 1 Row 2 Row 3 Row 4012345678910Main titleColumn 1 Column 2 Column 3Test BenchWaveformRegB LayoutDRC CheckLVS ReportExtracted WaveformExtracted Propogation TimeBasic Gates1. OR2: Designed the layout for the OR2 gate. input A Input B Output Y0 0 00 1 11 0 11 1 1•Control Inverter: this is the gating inverter which is used to drive the load, this design to drive a large load saves us the power and at the same area consumption. This inverter was designed to drive the worse load conditions of 150fF and a delay of .2ns.•this gives a hand calculation of :•Wn=7.8u M•Wp=13.95u M•Then after the parametric analysis, similar values of Wn and Wp were found, which came out to be Wn=7.8 and Wp=12.9 for same similar rise and fall times. Then the inverter design was modified by the team members and the test bench was run again to find the delay.•NAND2: designed and tested the schematic of the NAND2 for an expected load of 200fF•NAND3: designed and tested the schematic of the NAND2 for an expected load of