Systems I 15-319, spring 2010 4th Lecture, Jan 26th Lecture MotivationIntel Open Cirrus Cloud - PittsburghBlade PerformanceCloud PerformanceHow could these different bandwidths impact the Cloud’s performance?Single CPU Machine’s Component A Single-CPU Computer ComponentsThe Von Neuman machine - Completed 1952Slide Number 10MotherboardThe ProcessorCentral Processing UnitInstruction Set Architecture (ISA)Program ExecutionSynchronous Systems Processor Components (1/3) Processor LayoutProcessor Components (2/3) Processor Components (3/3) Instruction ProcessingISAProcessor-Memory GapMain MemoryLocalityProblem: Processor-Memory BottleneckSolutionThe Memory Hierarchy How does it work?Memory Design: HierarchyDiskDisk GeometryDisk Operation (Single-Platter View)Disk Access TimeLogical Disk BlocksI/O BusReading Disk Sector (1)Reading Disk Sector (2)Reading Disk Sector (3)Storage TrendsWhat is the Typical Bandwidth Between … ?What is the Typical Bandwidth Between Layers?RAID: Redundant Array of Inexpensive DisksNetworkInternal Computer Network (1/2)Internal Computer Network (2/2)Connection Between ComputersConnection Between ComputersConnection Between ComputersOSI ModelNetwork TopologiesNetwork TopologiesHow does it all work?Program Path to ExecutionFrom High Level (English) to Binary (Machine)What is Operating System?Role of the Operating SystemProcess ControlProcess Control Process SchedulingMemory Management File System ManagementI/O Subsystem ManagementCarnegie MellonSpring 2010 ©15-319 Introduction to Cloud ComputingIntroduction to Cloud ComputingMajd F. SakrSystems I 15‐319, spring 2010 4th Lecture, Jan 26thCarnegie MellonSpring 2010 ©15-319 Introduction to Cloud Computing2Lecture Motivation Overview of a Cloud architecture Systems review ISA Memory hierarchy OS Networks Next time Impact on cloud performanceCarnegie MellonSpring 2010 ©15-319 Introduction to Cloud ComputingIntel Open Cirrus Cloud ‐ PittsburghCarnegie MellonSpring 2010 ©15-319 Introduction to Cloud ComputingBlade Performance Consider bandwidth and latency between these layersL3MemoryQuad Core ProcessorDiskcorecorecorecoreL2Quad Core ProcessorcorecorecorecoreL2L1L1Carnegie MellonSpring 2010 ©15-319 Introduction to Cloud ComputingCloud Performance Consider bandwidth and latency of all layersCarnegie MellonSpring 2010 ©15-319 Introduction to Cloud ComputingHow could these different bandwidths impact the Cloud’s performance?To understand this, we need to go through a summary of the machine’s components?Carnegie MellonSpring 2010 ©15-319 Introduction to Cloud ComputingSingle CPU Machine’s Component ISA (Processor) Main Memory Disk Operating System NetworkCarnegie MellonSpring 2010 ©15-319 Introduction to Cloud ComputingA Single‐CPU Computer ComponentsMain MemoryDiskI/O BridgeI/O BusNetworkControlUnitRegister FileALUPCIRDatapathControlCPUCarnegie MellonSpring 2010 ©15-319 Introduction to Cloud ComputingThe Von Neuman machine ‐ Completed 1952 Main memory storing programs and data ALU operating on binary data Control unit interpreting instructions from memory and executing Input and Output equipment operated by control unitI/OSystemMMControlUnitRegister FileALUPCIRDatapathControlCPUCarnegie MellonSpring 2010 ©15-319 Introduction to Cloud ComputingALU & CUInput & OutputMThe Five Von Neumann Components12345Carnegie MellonSpring 2010 ©15-319 Introduction to Cloud ComputingMotherboard Everything is attached to it: CPU/ memory/ monitor/ mouse/ keyboard/ add‐on cards/ printers/ scanners/ speakers/ ..etcCarnegie MellonSpring 2010 ©15-319 Introduction to Cloud ComputingThe ProcessorMain MemoryDiskI/O BridgeI/O BusNetworkCPUCPUControlUnitRegister FileALUPCIRDatapathControlCarnegie MellonSpring 2010 ©15-319 Introduction to Cloud ComputingCentral Processing Unit The Brain: a functional unit that interprets and carries out instructions (does mathematical manipulation) Also called a Processor Contains tens of millions of tiny transistors http://www.overclock.net/intel-cpus/72887-broken-cpu-pins.htmlControlUnitRegister FileALUPCIRDatapathControlCarnegie MellonSpring 2010 ©15-319 Introduction to Cloud ComputingInstruction Set Architecture (ISA) Every processor has a unique set of operations (Instruction Set or Machine Instructions) Written in binary language called Machine Language Each Instruction consists of (operator & operands) Operand: data or a memory address of the data that we need to operate on Instructions Categories:Category ExampleArithmetic Add, subtract, multiply, divideLogic And, or, not, exclusive orProgram Control Branching, subroutinesData Movement Move, load, storeI/O Read, writeCarnegie MellonSpring 2010 ©15-319 Introduction to Cloud ComputingProgram Execution Fetch/Execute Cycle: Fetch Cycle: get instruction from memory Execute Cycle: Decode instruction, get operands, execute the operation on themRetrieve next Instruction from memoryRetrieve operands from memoryPerform the operationMaybe store results in memoryCarnegie MellonSpring 2010 ©15-319 Introduction to Cloud ComputingSynchronous Systems Each step waits for clock ticks to begin A 100 MHz processor uses a clock that ticks 100,000,000 times per secondRetrieve next Instruction from memoryRetrieve operands from memoryPerform the operationMaybe store results in memoryCycle Speed:millionths of a secondCarnegie MellonSpring 2010 ©15-319 Introduction to Cloud ComputingProcessor Components (1/3) ControlUnitRegister FileALUPCIRDatapathControlCarnegie MellonSpring 2010 ©15-319 Introduction to Cloud ComputingProcessor LayoutCarnegie MellonSpring 2010 ©15-319 Introduction to Cloud ComputingProcessor Components (2/3) Control Unit Processor’s Supervisor Connects and regulates the interaction between the datapath and memory. ControlUnitRegister FileALUPCIRDatapathControl Job Steps: Retrieve instruction from Memory Decode it Break it into a sequence of actions Carries out the execution of an instruction Program Counter (PC): has the address of the instruction to be fetched Instruction Register (IR): has the instruction most recently fetchedCarnegie MellonSpring 2010 ©15-319 Introduction to Cloud ComputingProcessor Components (3/3) Datapath Register Files:General purpose storage locations inside the processor that hold values or addresses Arithmetic Logic Units:
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