Clock SynchronizationSlide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Memories: SRAM and DRAMSlide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 311-Transistor Memory Cell (DRAM)Slide 33Slide 34Asynchronous CircuitsSlide 36Slide 37Slide 38Slide 39Slide 40Slide 41Slide 42Slide 43Slide 44Slide 45Slide 46Slide 47Slide 48Slide 49Slide 50Slide 51Slide 52Slide 53Slide 54Slide 55Slide 56Slide 57Slide 58Slide 59Slide 60Slide 61Slide 62Slide 63Slide 64Slide 65Slide 66Slide 67Slide 68Slide 69Slide 70Slide 71Slide 72Slide 73Slide 74Slide 75Slide 76Slide 77Slide 78Slide 79Slide 80Slide 81Slide 82Slide 83Slide 84Slide 85Slide 86Slide 87Clock SynchronizationTiming IssuesCompare the following implementations …Both attempt to “enable” the change in the D flip-flopIs one preferred over the other?Yes – the AND gate version is simpler but undesirableDQQDataClockED Q Q Q R Clock E 0 1Clock SkewIf a circuit uses many of each type, then the flip-flops with the AND gated clock will observe the change in the clock signal later than the othersGate delay in the AND gate causes a skew in the clock pulseThis can also happen if the lengths of the wires vary considerablyDQQDataClockED Q Q Q R Clock E 0 1 Avoid this!Clock Distribution NetworkTo ensure that all wires to flip-flops are of the same length, and that the skew (if any) is the same …Use an H-tree distribution networkClock ffffffffffffffffGlobal Clock / ResetPLDs use a common global clock wired to all flip-flopsNo gates used to slow the clock signalGlobal reset is also commonly providedTiming ParametersData to be clocked into a flip-flop must be stable before/after the clock edgetsu = setup time  input must be stable for tsu ns prior to clock edgeth = hold time  input must remain stable for th ns after clock edget sut h Clk D QMore Timing ParametersOutput from the flip-flop changes after a register delay of trdOutput from the flip-flop will appear on the output pin of the chip after an output delay time of todD Q DataClock Chip package pinA B t Clock t DataOut t odcombinational logictrdClock to Output TimingA typical “clock to output” change tco is given bytco = tClock + trd + tod = 1.5 ns + 1 ns + 2 ns = 4.5 nsThis is the time between an active edge of the Clock on the input pin of the chip to the time at which the output is observed on the output pin of the chipFlip-Flop Timing in a Chip (1)Suppose tData = 4.5 ns, tClock = 1.5 ns, and tsu = 3 nsData takes 4.5 ns to get from input pin to FF data input AClock takes 1.5 ns to get from input pin to FF clock input BData changes on the input pin 3 ns prior to the Clock edge on the input pin  setup time met (from this viewpoint)But at the FF inputs, there is 0 ns setup between A and B  setup time is violated!DataClock A 3ns 4.5ns 1.5ns BFlip-Flop Timing in a Chip (2)Need larger setup time from the viewpoint of the input pinsNeed 6 ns gap between change in Data and active clock edge at the input pinsDataClock A 6ns 4.5ns 1.5ns B 3ns setup time metAsynchronous InputsWhat do you do when the inputs to a circuit arrive asynchronously with respect to the clock?Maybe they are generated off the chipWorry about violating the setup/hold timesIf the setup/hold times are violated, the output of the FF may assume a voltage level that is neither 0 nor 1 Enters a metastable stateEventually enters 0 or 1, but can’t predict which nor whenHandling Asynchronous InputsNever do this …setup time violationunstable state!Q1 may manage to catch the Data, but Q2 may notSynchronizing Asynchronous Inputs (1)Use a data synchronizer to catch an asynchronous input and synchronize it when it first enters the systemNever allow asynch inputs to fan out to more than one FF in a systemdata synchronizerMay become metastable, but will recover as long as CCT is long enoughVery unlikely to ever become metastableSynchronous outputSynchronizing Asynchronous Inputs (2)Use this circuit when the input pulses will be > 1 clock period wideThe extra flip-flop guards against metastabilityCase 1: the data synchronizer FF goes metastable and eventually falls back to 0 Asynchronous input has been synchronizedSynchronizing Asynchronous Inputs (3)Case 2: the data synchronizer FF goes metastable and eventually rises to 1 Asynchronous input has been synchronizedSynchronizing Asynchronous Inputs (4)Use this circuit when the input pulses will be < 1 clock period wideGuards against metastabilityAllows for long pulses as well as short onesNote: multiple short pulses occurring within a single clock period will be missedDebouncing Asynchronous InputsAsynchronous inputs may also require “smoothing” to eliminate any glitches in the input due to mechanical “bouncing” of the signalA pushbutton input usually suffers from this problemNeed to detect the pushbutton input, but ignore the bounced signalAlso note that pushbuttons are active low, so it is convenient to invert the input signal to be active highMain idea: as soon as an input of 0 is detected, output a 1Only revert to 0 again after about 40 ms of continuous unasserted inputVerilog for Debouncing Inputs4 cycles @ 100Hz = 40 ms to debounce the pushbuttonTrimming the Input SignalDebounced inputs may also be asserted for >> 1 clock cycle due to external requirementsPushbutton may be manually held down for many cyclesIt may be desired to “trim” a multi-cycle input to a single cycle pulseAssume the input is already debounced (for simplicity)A/0B/1C/0000111Verilog for One Pulse SignalsMemories: SRAM and DRAMSRAMSRAM – static random access memoryWhen you need to store quite a large amount of data, registers are two expensiveSRAM blocks are 2D arrays of SRAM cellsAn SRAM cell stores 1 bit of informationA mxn SRAM block stores m items of n bits eachm:n is called the aspect ration is usually 8, 16, 32m is usually a power of 21 Bit SRAMSpace is at a premium, so SRAM must be smallUse very few transistorsDesign is based on the basic latch we designed earlierSel DataDataNot required, but often present6 transistors: (2 per NOT + 2)Writing to SRAMSel = 1 allows Data to be “written” into the feedback loopWhat