UCSB ECE 594 - Using a Miller Hold Capacitance (9 pages)

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Using a Miller Hold Capacitance



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Using a Miller Hold Capacitance

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Lecture Notes


Pages:
9
School:
University of California, Santa Barbara
Course:
Ece 594 - High Speed Mixed Signal & Communications IC design

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IEEE JOURNAL OF SOLID STATE CIRCUITS VOL 26 NO 4 APRIL 1991 643 A High speed Sample and Hold Technique Using a Miller Hold Capacitance Peter J Lim Student Member IEEE and Bruce A Wooley Fellow IEEE Abstract This paper introduces a circuit technique for increasing the precision of an open loop sample and hold circuit without significantly reducing the sampling speed With this technique the sampling error resulting from input dependent charge injection of the sampling switch is attenuated by sampling the input voltage onto a capacitance that is small during the sample mode but is in effect increased during the transition to the hold mode through the action of Miller feedback The technique thus allows for a high sampling speed without the precision penalty traditionally associated with open loop sample and hold circuits A sample and hold circuit based on the proposed approach has been designed and fabricated in a 1 pm CMOS technology and an order ofmagnitude reduction in the input dependent charge injection has been demonstrated experimentally This prototype circuit is capable of sampling an input to a precision of 8 b with an acquisition time of 5 ns The experimental sample and hold circuit operates from a single 5 V supply and dissipates 26 5 mW I INTRODUCTION A S DATA conversion systems continue to improve in speed and resolution increasing demands are placed on the performance of high speed sample and hold circuits The throughput of the fastest analog to digital converters is typically limited by the speed and precision with which the comparison function can be performed However the maximum input signal bandwidth that can be accommodated by a converter at a specified precision is governed by the speed and precision at which the input can be sampled In the highest speed moderate resolution 8 10 b fully parallel flash converters the use of an input sample andhold circuit avoids sensitivity of the conversion to mismatches in clock distribution to the large number of



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