IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, NO. 4, APRIL 1991 643 A High-speed Sample-and-Hold Technique Using a Miller Hold Capacitance Peter J. Lim, Student Member, IEEE, and Bruce A. Wooley, Fellow. IEEE Abstract -This paper introduces a circuit technique for increasing the precision of an open-loop sample-and-hold circuit without significantly reducing the sampling speed. With this technique, the sampling error resulting from input-dependent charge injection of the sampling switch is attenuated by sampling the input voltage onto a capacitance that is small during the sample mode but is, in effect, increased during the transition to the hold mode through the action of Miller feedback. The technique thus allows for a high sampling speed without the precision penalty traditionally associated with open-loop sample-and-hold cir- cuits. A sample-and-hold circuit based on the proposed approach has been designed and fabricated in a 1-pm CMOS technology, and an order-of- magnitude reduction in the input-dependent charge injection has been demonstrated experimentally. This prototype circuit is capable of sam- pling an input to a precision of 8 b with an acquisition time of 5 ns. The experimental sample-and-hold circuit operates from a single 5-V supply and dissipates 26.5 mW. I. INTRODUCTION S DATA conversion systems continue to improve in A speed and resolution, increasing demands are placed on the performance of high-speed sample-and-hold circuits. The throughput of the fastest analog-to-digital converters is typi- cally limited by the speed and precision with which the comparison function can be performed. However, the maxi- mum input signal bandwidth that can be accommodated by a converter at a specified precision is governed by the speed and precision at which the input can be sampled. In the highest speed, moderate-resolution (8-10 b) fully parallel (flash) converters, the use of an input sample-and- hold circuit avoids sensitivity of the conversion to mis- matches in clock distribution to the large number of com- parators, mismatches in delay through comparator input stages, and RC delays in the input resistor ladder [1]-[3]. In multistep converter architectures, the need for an input sample-and-hold function is even more important because of the delays associated with quantizing the input in two or more stages. As yet, monolithic implementations of sample- and-hold systems that meet the stringent requirements for high-speed systems are complex in design and are usually fabricated in hybrid technologies. In order to meet the stringent performance requirements for high-speed data acquisition in an economic monolithic implementation, a circuit technique has been devised to increase the resolution of an open-loop sample-and-hold Manuscript received September 4, 1990; revised December 4, 1990. This work was supported by the U.S. Army Research Office under Contract DAAL03-87-K-0111. The authors are with the Center for Integrated Systems, Stanford University, Stanford, CA 94305. IEEE Log Number 9042467. circuit without the need for precise capacitors or an increase in capacitor size, which would result in a corresponding decrease in sampling rate. In this proposed approach the input is sampled onto an equivalent hold capacitance that is small during the sampling mode but is increased during the hold mode by means of Miller feedback. A sample-and-hold circuit based on the approach has been designed and fabri- cated in a 1-pm CMOS technology, and an order-of-magni- tude reduction in the input-dependent charge injection of the sampling switch has been verified experimentally. The prototype circuit is capable of sampling a voltage input to a precision of 8 b within an acquisition time of 5 ns. The experimental sample-and-hold circuit operates from a single 5-V supply and uses clock signals that are buffered via on-chip inverters. In Section 11, several alternative sample-and-hold architec- tures are examined. The proposed sample-and-hold tech- nique is then introduced in Section 111. An analysis of the channel charge injection mechanism of MOS transistors dur- ing turn-off is also presented. Experimental results from a prototype implementation of the proposed sample-and-hold circuit are included in Section IV. 11. SAMPLE-AND-HOLD IMPLEMENTATION A. Architectures Two basic circuit configurations commonly used to imple- ment monolithic sample-and-hold circuits are the open-loop and closed-loop topologies shown in Figs. 1 and 2, respec- tively. The open-loop architecture potentially offers the fastest implementation of the sampling function [4]-[6]. In its simplest form, an open-loop sample-and-hold circuit consists of a switch, shown implemented with MOS pass transistor M1, which samples the input onto a hold capacitance CHOLD. A high-input-impedance unity-gain amplifier buffers the hold capacitance and provides a low-impedance output node that drives the succeeding circuitry. During the sample mode, the sampling switch M1 is closed and the voltage across capaci- tor settles to the input voltage level. However, in the transition from the sample mode to the hold mode, the turn-off of the sampling switch results in charge injection effects that introduce a pedestal error AVs at the output, as illustrated in Fig. 1. In designs where an MOS transistor functions as the sampling switch, input-dependent charge injection associated with the fast turn-off of the switch is often the principal source of sampling error [7]-[9]. This pedestal error results in gain error and introduces nonlinear- ity that distorts the sampled signal. Since the pedestal error 0018-9200/91/0400-0643$01.00 01991 IEEE644 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, NO. 4, APRIL 1991 In , M1 C HOLD 7 Output -lTlx Sample Fig. 1. Open-loop sample-and-hold architecture. Fig. 2. Closed-loop sample-and-hold architecture. is not well-controlled, it is difficult to compensate for this error using self-calibration techniques. Several closed-loop architectures avoid input-dependent charge injection during turn-off of the sampling switch [6]. One such configuration is shown in Fig. 2. In this circuit, the sampling switch is always at virtual ground during sampling. This