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SJSU EE 166 - Final Exam

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EE 166: Final Exam NAME: 1Question 1 (20 PTS): You are designing a FLIP FLOP that uses three input NAND GATES that have both reset and set. You know that the reset and set pins will hardly ever be used to set or reset the circuit. Which pins do you put the set or reset on to make the circuit as fast as possible? You do not need to know the exact structure of the FF. Explain why for full credit.EE 166: Final Exam NAME: 2 Question 2 (10PTS): Which circuit will have the fastest fall time? Why? Which circuit will have the slowest fall time? Why?EE 166: Final Exam NAME: 3Question 3 (50PTS): Below is a circuit that needs to run at 200MHz. Describe how you would go about making sure that the circuit can function at this speed. Fill out the table for all logic levels including the ones inside the DFF (Use the DFF circuit you used in your project.) Show which equation you would use for each logic level (propagation delay or rise/fall time). This is just like in class but do not solve for Cg or Wn WP. Explain the process you would go through to find WN WP for each gate. Logic Level Type of Gate #CDNs #CDP’s #Parallel PMOS #Parallel NMOS #Series PMOS #Series NMOS Equation (Propagation delay or rise/fallEE 166: Final Exam NAME: 4EE 166: Final Exam NAME: 5EE 166: Final Exam NAME: 6 Question 4 (20PTS): Draw a set of test vectors that will demonstrate a set up error on a DFF with a setup and hold time of 2ns.EE 166: Final Exam NAME: 7Question 5 (20PTS): Using the AOI technique design a CMOS circuit to implement the following logic function: Z=(AB+C+DEF)G Show the PNET and the NNET connected into a circuitEE 166: Final Exam NAME: 8Question 6 (10PTS): Using the Euler path method come up the order of the inputs for the circuit in question 5. (5pts.) Show stick diagram (5pts)EE 166: Final Exam NAME: 9EE 166: Final Exam NAME: 10Question 7 (20PTS): Describe in detail what the source/sources of clock skew are:EE 166: Final Exam NAME: 11Question 8 (10PTS): You have designed a Schmitt trigger to have the following properties: a) low to high trip of 4.0V. b) high to low trip of 1.0V. Draw the response of a ST, over the graph below. TIMEVOLTAGE5410VIN to STEE 166: Final Exam NAME: 12Question 9 (10PTS): Design a circuit that will drive the clock pin on 200 DFFs. Each DFF has a CIN of 10fF that will minimize the delay. Assume that WN=1.5μm and WP=3μm of the inverter that has to be buffered. Assume:  α=3.0  Frequency=200MHz What is the power used by your circuit?EE 166: Final Exam NAME:


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SJSU EE 166 - Final Exam

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