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comparison-of-DES-algorithm-xun-yang



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Comparison of DES Algorithm Implemented in FPGA and NIOS Soft Core Jason Cong Xun Yang VLSI CAD Lab Computer Science Department UCLA Total logic elements Total Pins Total ESB bits Working Frequency MHz RSA hardware implementation synthesized with Leonardo Spectrum 3 877 20 8 384 DES hardware implementation synthesized with Leonardo Spectrum Not available clock skew data delay 2 744 185 32 768 47 4 47 4M 3 173 109 60 448 33 333 CPU 19 0K DES NIOS software implementation Throughput 64bit s Nios Architecture The Nios embedded processor is a general purpose RISC CPU implemented as a soft core in Altera APEX 20K devices The Nios family includes a 32 bit and a 16 bit processor core Includes the industry standard GNUPro software from Cygnus Nios 32 bit Nios 16 bit Data bus size bits 32 16 ALU width bits 32 16 Internal register width bits 32 16 Address bus size bits 33 17 Instruction size bits 16 16 Logic cells typical 1 700 1 100 fMAX EP20K200E 1 device Up to 50 MHz Up to 50 MHz Nios Embedded Processor Experiment Condition RSA DES hardware implementation RTL description synthesized with Leonardo Spectrum then mapped result is given to Quartus in EDF for placement and route Experiment Condition des NIOS software implementation NIOS 32bit processor is configured in Quartus including 1K ROM bit width is 32 4K RAM 256K external RAM 1M external Flash 4 PIO for button led lcd and seven segment digital display 1 UART The configured processor is synthesized with Leonardo Spectrum then mapped result is given to Quartus for placement and route



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