3 5 r 3 5 r 3 5 r 3 8 5 r 3 5 r 3 5 b Non Negligible Propagation Delay r a Negligible Propagation Delay 8 8 r r Impact of Delays Review of Last lecture CSMA CSMA CD Ethernet Scheduling approaches to MAC Polling and Reservations Token ring 3 3 5 5 ELEN602 Lecture 12 8 8 r r 3 3 t 3 t 1 b a r d 3 d r M d Outbound line Shared inbound line c d Each station has own minislot for making reservations 1 frame d Examples of Polling Systems 1 2 1 frame d Data Transmissions Central Controller Central Controller r Reservation interval Basic Reservation System 4 2 time 1 E T E X 0 2 4 6 8 10 12 14 16 18 20 0 2 0 1 M 0 3 0 4 E X 0 5 0 6 0 7 0 8 0 9 Packet Delay for Polling a 0 2 4 5 packet transmissions 3 polling messages 1 Polling Messages and Transmission 0 5 0 1 10 5 2 7 5 t Wait for packets ahead in the queue to be transmitted Wait for the station to be polled Actual Packet transmission delay Packet Propagation delay input from ring delay listen mode output to ring delay 8 from device transmit mode to device Token passing Rings 6 Actual Packet transmission delay Walking time for polling When channel utilization is low we need to still pay the walking time delay Performance depends on the ratio of total walk time to the average service time Delays in Polling dd d d d received back token back Free token last data bit is Busy token receiving the busy dd d d d d d Insert token after d d d c Single Packet Insert token after b Single Token 0 10 20 30 40 50 0 0 1 0 2 0 3 0 4 RHO 0 5 10 0 6 0 7 0 8 0 1 1 0 9 0 Mean Waiting time M 32 unlimited service token AVG WAIT bit is sent Insert token after last data a Multitoken Token Reinsertion Strategies 11 9 0 0 4 0 8 1 2 Single Packet Operation M 10 1 6 2 M 50 2 4 2 8 3 2 3 6 4 4 4 M 10 M 50 4 8 a Single Token Operation Multiple Token Operation 0 10 20 30 40 50 0 0 1 0 2 0 3 0 4 0 5 RHO 0 6 0 1 1 0 7 0 8 10 0 9 0 Mean waiting time multitoken ring one packet token 0 0 2 0 4 0 6 0 8 1 1 2 Throughput for single packet per token schemes AVG WAIT Maximum Throughput 12 10 Low Latency Ring A A High Latency Ring t 0 A begins frame b t 0 A begins frame a 0 0 1 10 0 2 0 3 0 4 1 0 5 RHO 0 6 0 7 0 1 0 8 0 9 0 t 400 last bit of frame enters ring A t 90 return of first bit A t 840 return of first bit A t 400 transmit last bit A 13 t 0 A begins frame t 1240 reinsert 15 token High Latency Ring A b C A Wiring center Token Ring Star Topology D t 400 transmit last bit A t 90 return of first bit A t 840 arrival first frame bit A t 210 return of header A E A 14 t 960 reinsert 16 token A t 400 last bit enters ring reinsert token Reinsert token after frame header 120bits returns Low Latency Ring A t 0 A begins frame a B A t 490 reinsert token A Ring Latency M 20 R 4Mbps d 100m b 2 5bits v 2x10 8 0 10 20 30 40 50 Mean waiting time single packet token ring AVG WAIT AC A xx A C x x E 4 ED 1 FS 1 intermediate frame bit error detection bit A address recognized bit xx undefined C frame copied bit I E FF frame type ZZZZZZ control bit 19 17 PPP Priority T Token bit M Monitor bit RRR Reservation J K non data symbols line code FDDI Token Rotation C I 0 ED Information FCS AC Allows synchronous and asynchronous data to be transmitted Synchronous traffic is limited to Si time units per station Each station maintains a Token Rotation Timer TRT Token Holding time THT TTRT TRT where TTRT is Target Token Rotation Time If THT 0 station transmits all synchronous traffic Can transmit asynchronous traffic until total time THT If THT 0 station transmits only synchronous traffic Frame status J K 1 J K 1 Ending delimiter Z Z Z Z Z Z FF 0 M RRR Frame control T J K 0 J K 0 2 or 6 Source Address PPP FC 2 or 6 Destination Address Access control Starting delimiter SD Data Frame Format 1 1 1 SD IEEE 802 5 Token and Data Frames Token Frame Format C 1 2 or 6 Destination Address CLFFZZZZ FC 1 FC 4 ED Information FCS SD ED 1 1 FS E C Synch Asynch L Address length 16 or 48 bits FF LLC MAC control reserved frame type 2 or 6 Source Address PRE 5 bit buffer Max clock difference Symbol frequence 0 01 125M 0 4ms In 0 4ms 0 4 125M 50 000 bits Actual data bits 40 000 with 4B5B coding Frame Size 36 000 bits to allow clock differences of upto 0 005 Frame Control PRE SD Preamble 8 Token Frame Format Data Frame Format D FDDI Frame Structure Typically used as a Campus Backbone B FDDI Dual ring Network A 20 18